GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: kee1741042160142
Ixiasoft
Visible to Intel only — GUID: kee1741042160142
Ixiasoft
5.7. Connecting the Reference Clock Buffer Status to the GTS Reset Sequencer Intel® FPGA IP
Each non- PCIe* IP has one reference clock buffer failed status port o_refclk_bus_out to indicate the status of the reference clock for that side of the device. For multiple IP applications, only one port needs to be connected to the GTS Reset Sequencer Intel® FPGA IP. You can choose which IP is connected GTS Reset Sequencer Intel® FPGA IP and leave the rest unconnected.