GTS CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 814583
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide

2.2.2. Round Trip Counter

A Round Trip Counter is a simple counter that measures the duration between two pulses. The pulses are always in pairs, called as start, and stop pulse. The pulses are generated by the TX pattern generator and RX pattern checker, respectively. When a start pulse is received, it triggers a counter to start counting. When a stop pulse is received, the counter stops.

The counter value is the number of clock cycles elapsed between the two pulses. To calculate duration in unit time, multiply the counter value by the period of the clock cycle. For accuracy, you can repeat this process multiple times (using a parameter) and obtain the mean average. This average duration between start and stop pulses is called the round trip delay. The round trip delay can be used as a benchmark to check against the Deterministic Latency measurement of GTS CPRI PHY Intel FPGA IP, which has its own independent measurement. The two measurements must not differ by +/- 3ns.
Table 13.  Round Trip Counter Parameter
Parameter Name Default Value Description
COUNT_WIDTH 8 Determines the width of counter_out.
DL_TOT_MEASURE_CNT 10 Determines how many pairs of start and stop pulses must be received before asserting measure_done.
Table 14.  Round Trip Counter Ports
Port Name Width Direction Domain Description
clk 1 Input - Clock. Supply with sampling_clk.
reset 1 Input clk Synchronous Reset. Active high.
cpri_rate_sel 4 Input clk Indicates the current CPRI rate to the block. This port follows the same definition as the F-Tile CPRI PHY Intel FPGA IP.
start 1 Input clk Start pulse to start the internal counter.
stop 1 Input clk Stop pulse to stop the internal counter.
measure_done 1 Output clk An indicator that is asserted when a set number of pairs of start/stop pulses (specified by DL_TOT_MEASURE_CNT) have been received.
trigger_recount 1 Output clk An indicator that is asserted when a start and stop pulse pair is received, and RT counter is ready to receive the next pair.
counter_out COUNT_WIDTH Output clk The total duration of all the start and stop pulses in terms of clock cycles.
The following calculates calculate the round trip delay: 
Round Trip Delay = (counter_out * clk period) / DL_TOT_MEASURE_CNT
where:
  • clk period = sampling_clk period = 1/250 MHz = 4ns
  • DL_TOT_MEASURE_CNT = 128 (for hardware) or 32 (for simulation)
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