GTS CPRI PHY Intel® FPGA IP Design Example User Guide

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ID 814583
Date 3/31/2024
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives 4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Generating the Design 1.3. Directory Structure 1.4. Simulating the Design Example Testbench
2. Design Example Description x
2.1. Features 2.2. Design Example Components 2.3. Simulation Design Example 2.4. Hardware Design Example 2.5. Interface Signals 2.6. Design Example Registers
2.2. Design Example Components x
2.2.1. Packet Client 2.2.2. Round Trip Counter 2.2.3. Sources and Probes 2.2.4. Avalon® Memory-Mapped Decoder 2.2.5. JTAG Host 2.2.6. IOPLL 2.2.7. System PLL 2.2.8. Reset Sequencer
1. Quick Start Guide
2. Design Example Description
3. GTS CPRI PHY Intel® FPGA IP Design Example User Guide Archives
4. Document History for GTS CPRI PHY Intel® FPGA IP Design Example User Guide

2.4. Hardware Design Example

Figure 6. Block Diagram
The GTS CPRI PHY Intel® FPGA IP core hardware design example includes the following components:
  • GTS CPRI PHY Intel® FPGA IP core.
  • Packet client logic block that generates and receives traffic.
  • Round trip counter.
  • IOPLL to generate the sampling clock for deterministic latency logic inside the IP, and the round trip counter component at testbench.
  • System PLL to generate the system clocks for the IP.
  • Avalon® memory-mapped address decoder to decode reconfiguration address space for CPRI PHY Reconfiguration Interface, PMA Avalon® Memory-Mapped Interface, and Datapath Avalon® Memory-Mapped Interface.
  • Sources and probes for asserting resets and monitoring the clocks and a few status bits.
  • JTAG controller that communicates with the System Console. You communicate with the client logic through System Console.
  • GTS Reset Sequencer Intel FPGA IP together with The Soft Reset Controller (SRC) handles all non-PCIe reset scheduling and sequencing for the Agilex™ 5 FPGAs.
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