MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.2. Simulating the Design

The provided testbench simulates the MIPI CSI-2 IP transmitter and receiver, running in loopback mode. A fast loopback simulation model replaces the MIPI D-PHY, which this simulation bypasses.

The input to and the output from the DUT is AXI4-Stream. When not running in passthrough mode this complies with the Intel FPGA Streaming Video Protocol Specification.

The testbench follows a standard structure, where a source generates stimulus that passes into the DUT. Then the output of the DUT passes into a sink that checks the received signals and data.

Because MIPI CSI-2 is an image transport standard, the source generates image frames as a series of pixel data packets and required control packets. The sink checks that the data and signals received exactly match what was sent by the source.

The stimulus provided creates 10 small image frames with a resolution of 128x96.

The parameters used for the testbench, such as number of MIPI lanes and image format, match those you chose when creating the IP.

Figure 3. Design Simulation Flow
  1. Navigate to the simulation directory of your choice.
  2. Run the simulation script for the supported simulator. The script compiles and runs the testbench in the simulator.
  3. Analyze the results.
A successful simulation ends with the following message: 
# ed_sim_tb: 

# ed_sim_tb: SUCCESS: Test has completed! 

# Simulation passed 

# ** Note: $finish    : ../../ed_sim_tb.sv(150) 

#    Time: 2096585 ns  Iteration: 0  Instance: /ed_sim_tb 

# End time: 23:47:25 on Mar 20,2024, Elapsed time: 0:01:14 

# Errors: 0, Warnings: 5217
Table 2.  Steps to Run Simulation
Simulator Working Directory Instructions
Questasim /ed_sim/sim/mentor In the command line, type vsim -c -do sim.do.
Riviera-PRO /ed_sim/sim/aldec In the command line, type vsim -c -do sim.do..
VCS MX /ed_sim/sim/synopsys/vcsmx In the command line, type source sim.sh.
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