MIPI CSI-2 Intel® FPGA IP Design Example User Guide

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ID 813931
Date 7/26/2024
Public
Document Table of Contents
Document Table of Contents x
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide 2. MIPI CSI-2 Intel® FPGA IP Design Example 3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide x
1.1. Generating the Design 1.2. Simulating the Design 1.3. Directory Structure 1.4. Compiling the Design
1.1. Generating the Design x
1.1.1. Design Example Parameters
2. MIPI CSI-2 Intel® FPGA IP Design Example x
2.1. Agilex™ 5 MIPI CSI-2 RX+TX Features 2.2. Agilex™ 5 MIPI CSI-2 RX-only Design Features 2.3. Software Requirements 2.4. Functional Description 2.5. Simulation
2.4. Functional Description x
2.4.1. Design Components 2.4.2. Reset Scheme 2.4.3. Clocking Scheme
2.5. Simulation x
2.5.1. Data Signal Checking 2.5.2. Verification 2.5.3. Display Messages 2.5.4. Waveform Plotting 2.5.5. Structure 2.5.6. Known Limitations
2.5.5. Structure x
2.5.5.1. Top Level Testbench 2.5.5.2. Device Under Test (DUT) Wrapper 2.5.5.3. PHY-Protocol Interface (PPI) Loopback 2.5.5.4. Test Generator
1. MIPI CSI-2 Intel® FPGA IP Design Example Quick Start Guide
2. MIPI CSI-2 Intel® FPGA IP Design Example
3. Document Revision History for the MIPI CSI-2 Intel® FPGA IP Design Example User Guide

1.3. Directory Structure

The Quartus® Prime software generates the MIPI CSI-2 IP design example files in the following directories:
Table 3.  Generated Files in Quartus® Prime Directory and File Description
File Description
quartus The directory that contains Quartus® Prime output files, including Quartus® Prime compilation reports.
csi2_dphy_sys.qpf Quartus Prime project file.
csi2_dphy_sys.qsf Quartus Prime .qsf assignment file.
Table 4.  Generated Files in RTL Directory and File Description
Directory or File Description
rtl The directory for each synthesizable component including Platform Designer (Standard) generated IPs.
csi2_dphy_sys.qsys Platform Designer file that contains CSI-2 RX and DPHY configuration.
rtl/csi2_dphy_sys The directory that contains Platform Designer generated directory.
csi2_dpy_sys/synth/csi2_dphy_sys.v Top-level subsystem wrapper Verilog file.
rtl/ip The directory that contains all IP files and IPs Platform Designer generated directory.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rx.ip IP file for MIPI CSI-2 RX.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx.ip IP file for MIPI CSI-2 TX.
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy.ip IP file for MIPI D-PHY.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0.ip IP file Reset Release.
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge.ip IP file Clock Bridge for AXI4S Clock.
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge.ip IP file Clock Bridge for DPHY Clock.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_rxsynth/csi2_dphy_sys_csi2_rx.v MIPI CSI-2 RX IP wrapper Verilog file.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_tx/synth/csi2_dphy_sys_csi2_tx.v MIPI CSI-2 TX IP wrapper Verilog HDL file.
ip/csi2_dphy_sys/csi2_dphy_sys_mipi_dphy/synth /csi2_dphy_sys_mipi_dphy.v MIPI D-PHY IP wrapper Verilog HDL file.
ip/csi2_dphy_sys/csi2_dphy_sys_csi2_reset_release_0/synth/ csi2_dphy_sys_csi2_reset_release_0.v Reset Release IP wrapper Verilog HDL file.
ip/csi2_dphy_sys/csi2_dphy_sys_axi_clock_bridge/synth/ csi2_dphy_sys_axi_clock_bridge.v AXI4S Clock Bridge IP wrapper Verilog HDL file.
ip/csi2_dpy_sys/csi2_dphy_sys_dphy_clock_bridge/synth/ csi2_dphy_sys_dphy_clock_bridge.v DPHY Clock Bridge IP wrapper Verilog HDL file.
Table 5.  Generated Files in Simulation Directory and File Description
Directory / File Description
ed_sim/ed_sim_tb.sv Top-level testbench file.
ed_sim/dut_wrapper.sv Wrapper around MIPI CSI-2 TX, RX and PPI Loopback.
ed_sim/cfg_pkg.sv SystemVerilog package containing generated IP Core parameters.
ed_sim/sim.spd File used by Quartus ip-make-simscript.
ed_sim/hdl/ Contains Encrypted Verification IP files.
ed_sim/sim/aldec Contains Riviera simulator script.
aldec/sim.do Script for Riviera simulation.
aldec/rivierapro_setup.tcl Setup file for Riviera simulation.
ed_sim/sim/mentor Contains Mentor simulator script.
sim.do Script for Modelsim simulation.
msim_setup.tcl Setup file for Modelsim simulation.
ed_sim/sim/synopsys/vcsmx Contains Synopsys VCSMX simulator script.
vcsmx/sim.sh Script for VCS simulation
vcsmx/vcsmx_setup.sh Script for VCSMX simulation.
vcsmx/synopsys_sim_setup.sh Setup file for VCSMX simulation.
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