MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 4/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interface Overview 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resource Utilization 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PHY Protocol Interface (PPI) Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Streaming Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PHY-Protocol Interface (PPI) Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for Intel® FPGA IP Cores and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PHY Protocol Interface (PPI) Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

5.2. MIPI CSI-2 Transmitter

Figure 6. MIPI CSI-2 Intel® FPGA IP Transmitter Block Diagram

The MIPI CSI-2 TX component consists of multiple layers defined in the MIPI CSI-2 specification version 3.0, such as the pixel to byte conversion, low level protocol and lane management layer.

The AXI to Clocked Video convertor (AXI2CV) receives video in the Intel FPGA Streaming Video Protocol via AXI4-Stream and converts it to clocked video format.

In video mode, the MIPI CSI-2 TX component converts the video data into the selected CSI-2 video data type and wraps it in CSI-2 packets according to the defined low-level protocol, adding synchronization packets as required. Long packet checksums and header ECC values are calculated and inserted to allow detection or correction of transmission errors.

In passthrough mode, it receives MIPI CSI-2 packets on an AXI4-Stream input interface from the user logic, and the video mode processing is bypassed.

The CSI-2 packets are distributed across the MIPI data lanes and presented to the MIPI D-PHY Intel® FPGA IP via the standard PHY-Protocol Interface (PPI).

Each component has an Avalon® memory-mapped interface register interface for control and status register access and will be given an address space. The most significant bit of the offset addresses from the system base address are 0x0 for the MIPI CSI-2 TX component and 0x1 for the AXI2CV component.
Table 25.  Top Level Interfaces
Interface Description
AXI4-Stream Intel FPGA Streaming Video (Full Variant) input

Carries pure video packet in Intel FPGA streaming video format. Includes Image Information Packet (IIP) and End of Field (EOP) packets.

Present only when Video mode enabled.
AXI4_Streaming MIPI Packet

AXI4-Stream input interface carrying MIPI CSI-2 packets.

Present only when Passthrough mode enabled.
TX PPI PHY-Protocol Interface. Refer to MIPI D-PHY specification version 2.5 Annex A.
Avalon® memory-mapped interface CSR Control and Status Register.
Figure 7. MIPI CSI-2 Intel® FPGA IP Transmitter (Video Mode)
Figure 8. MIPI CSI-2 Intel® FPGA IP Transmitter (Passthrough Mode)
Table 26.  MIPI CSI-2 Transmitter Functional Blocks
Functional Block Description
AXI2CV
  • Receives AXI4S Video Streaming Protocol (full variant) data and converts to clocked video data for the MIPI CSI-2 TX submodule.
  • Generates synchronization short packets for insertion into the CSI-2 data stream around the video packets
  • Supports multiple channels – arbitrates between input channels in round-robin order. The channel number will be used to set the virtual channel ID in the MIPI CSI-2 data stream.
Pixel-to-Byte Converter
  • Converts the video data from pixel format to the selected MIPI CSI-2 data type as defined in the CSI-2 specification.
  • Packs pixel data into bus with width that ensures that the MIPI link can be fully occupied.
Packet Arbiter Multiplexes synchronization short packets, video long packets and generic short packets into a single stream.
Error Correction Code (ECC) Calculates the ECC code for each packet header.
Packetizer
  • Applies long packet header.
  • Long packet payload CRC is calculated and appended after payload.
Lane Distributor Distributes the bytes from the incoming packet stream onto the configured number of MIPI lanes according to the CSI-2 specification.
Scrambler When configured this applies the CSI-2 LFSR scrambling function to long packet payloads to avoid any long periods of fixed signaling when the video data is constant.
TX PPI Performs handshaking with D-PHY IP to transmit CSI-2 packets.
Control and Status Register
  • MIPI CSI-2 TX and AXI2CV submodules each have their own CSRs.
  • ACSR Control MUX resides at the higher layer to multiplex the control operation between both CSRs.
  • The most significant bits of the address select between accessing the MIPI CSI-2 TX and CV2AXI CSRs.
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