MIPI CSI-2 Intel® FPGA IP User Guide

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ID 813926
Date 4/26/2024
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Document Table of Contents
Document Table of Contents x
1. About the MIPI CSI-2 Intel® FPGA IP 2. MIPI CSI-2 Intel® FPGA IP Interface Overview 3. MIPI CSI-2 Intel® FPGA IP Parameters 4. Designing with the MIPI CSI-2 Intel® FPGA IP 5. MIPI CSI-2 Intel® FPGA IP Block Descriptions 6. Registers 7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide
1. About the MIPI CSI-2 Intel® FPGA IP x
1.1. MIPI CSI-2 Intel® FPGA IP Features 1.2. Device Family Support for MIPI CSI-2 Intel® FPGA IP 1.3. Recommended Speed Grades 1.4. MIPI CSI-2 Intel® FPGA IP Performance and Resource Utilization 1.5. Release Information for MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview x
2.1. MIPI CSI-2 Intel® FPGA IP Clocks 2.2. MIPI CSI-2 Intel® FPGA IP Resets 2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces
2.3. MIPI CSI-2 Intel® FPGA IP User Interfaces x
2.3.1. Receiver PHY Protocol Interface (PPI) Signals 2.3.2. Avalon® Memory-Mapped Interface Control Interface Signals 2.3.3. Receiver AXI4-Streaming Output Video Interface Signals 2.3.4. Receiver AXI4-Stream Output Passthrough Interface 2.3.5. Transmitter PHY-Protocol Interface (PPI) Signals 2.3.6. Transmitter AXI4-Stream Input Video Interface Signals 2.3.7. Transmitter AXI4-Stream Input Passthrough Interface
4. Designing with the MIPI CSI-2 Intel® FPGA IP x
4.1. Generating the MIPI CSI-2 Intel® FPGA IP 4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition 4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation
4.2. MIPI CSI-2 Intel® FPGA IP Generation Output Quartus® Prime Pro Edition x
4.2.1. Files Generated for Intel® FPGA IP Cores and Platform Designer Systems
4.3. MIPI CSI-2 Intel® FPGA IP Systems Integration and Implementation x
4.3.1. D-PHY PHY Protocol Interface (PPI) Clock Frequencies 4.3.2. MIPI CSI-2 Receiver Clock Requirements 4.3.3. MIPI CSI-2 Transmitter Clock Requirements 4.3.4. Required Supporting IP 4.3.5. Limitations and Known Issues
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions x
5.1. MIPI CSI-2 Receiver 5.2. MIPI CSI-2 Transmitter
6. Registers x
6.1. CSI-2 Receiver Register Map 6.2. CSI-2 Transmitter Register Map
1. About the MIPI CSI-2 Intel® FPGA IP
2. MIPI CSI-2 Intel® FPGA IP Interface Overview
3. MIPI CSI-2 Intel® FPGA IP Parameters
4. Designing with the MIPI CSI-2 Intel® FPGA IP
5. MIPI CSI-2 Intel® FPGA IP Block Descriptions
6. Registers
7. Document Revision History for MIPI CSI-2 Intel® FPGA IP User Guide

2.3.7. Transmitter AXI4-Stream Input Passthrough Interface

This interface is intended to carry MIPI CSI-2 packets in the same format as those produced by the CSI-2 Receiver Output Passthrough interface. This allows retransmission of received MIPI CSI-2 packets, for example in bridging applications where multiple incoming CSI-2 streams are combined into a single outgoing CSI-2 stream.

One AXI4-Stream interface is provided per configured virtual channel. When multiple channels are enabled the virtual channel ID in the outgoing packet headers are updated according to the AXI4-Stream channel where the packet is presented. When a single channel is enabled the virtual channel ID in the packet headers is passed through unaltered, so this configuration can either be used in single-channel systems or cases where a merged multi-channel stream is already formed.

Note that when multiple channels are enabled, these are multiplexed at the input to the CSI-2 IP. No buffering is present at the inputs, so the user system must be designed to consider the periods of back-pressure on each channel while other channels are serviced, for instance by including a FIFO in the pipeline to each channel input.

Table 16.  Transmitter AXI4-Stream Input Passthrough Interface Signals num_VCs indicates the number of virtual channels configured in the IP and channel_width = PPI_data_width × lane_count
Signal Width Direction Description
axi4s_mipi_in_tdata num_VCs × channel_width Input MIPI packet data. VC0 data are placed in the least-significant channel_width bits, with the highest configured VC in the most significant bits.
axi4s_mipi_in_tkeep num_VCs × (channel_width ÷ 8) Input MIPI packet tkeep. VC0 signals are placed in the least-significant channel_width÷8 bits, with the highest configured VC in the most significant bits.
axi4s_mipi_in_tvalid num_VCs Input MIPI packet datavalid. VC0 signals are placed in the least-significant bit, with the highest configured VC in the most significant bit.
axi4s_mipi_in_tuser num_VCs Input

Bit0: AXI4-Stream start of packet

0 = Not start of packet

1 = Start of packet

VC0 signals are placed in the least-significant bit, with the highest configured VC in the most significant bit.
axi4s_mipi_in_tlast num_VCs Input AXI4-Streamend of packet. VC0 signals are placed in the least-significant bit, with the highest configured VC in the most significant bis.
axi4s_mipi_in_tready num_VCs Output AXI4-Streamdata ready. VC0 signals are placed in the least-significant bit, with the highest configured VC in the most significant bit.
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