Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

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ID 813775
Date 10/02/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs 7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
1. Overview x
1.1. Benefits of Using CvP 1.2. CvP System 1.3. CvP Modes
1.3. CvP Modes x
1.3.1. CvP Limitations
1.3.1. CvP Limitations x
1.3.1.1. CvP Error Recovery
2. CvP Description x
2.1. Configuration Images 2.2. CvP Modes 2.3. Compression Features 2.4. Pin Description
2.2. CvP Modes x
2.2.1. CvP Initialization Mode 2.2.2. CvP Update Mode
3. CvP Topologies x
3.1. Single Endpoint 3.2. Multiple Endpoints
4. Design Considerations x
4.1. Designing CvP for an Open System 4.2. Designing CvP for a Closed System
4.1. Designing CvP for an Open System x
4.1.1. FPGA Power Supplies Ramp Time Requirement 4.1.2. PCIe Wake-Up Time Requirement
4.1.2. PCIe Wake-Up Time Requirement x
4.1.2.1. For CvP Initialization Mode 4.1.2.2. For CvP Update Mode
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

2.4. Pin Description

The following table lists the CvP pin descriptions and connection guidelines:
Table 2.  CvP Pin Descriptions and Connection Guidelines
Pin Name Pin Type Pin Description Pin Connection SDM_IO Pins
CVP_CONFDONE Output The CVP_CONFDONE pin indicates the device has received the complete bitstream during configuration via protocol (CvP) core image configuration.

When used for this purpose, enable this pin using the Quartus® Prime software.

Connect this output pin to an external logic device that monitors the CvP operation. The VCCIO_SDM power supply must meet the input voltage specification of the receiving side.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16
INIT_DONE Output The INIT_DONE pin indicates the device has enter user mode upon completion of configuration. To use INIT_DONE to indicate user mode entry, you must enable it in the Quartus® Prime software.

When the INIT_DONE function is enabled, this pin drives high when configuration is completed and the device goes into user mode.

Intel recommends you to use SDM_IO0 or SDM_IO16 to implement the INIT_DONE function when available as it has an internal weak pull-down for the correct function of INIT_DONE during power up.

If SDM_IO0 and SDM_IO16 are unavailable, the INIT_DONE function can also be implemented using any unused SDM_IO pins provided that an external 4.7 kΩ pull-down resistor is provided for the INIT_DONE signal.

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16
CONF_DONE Output The CONF_DONE pin indicates all configuration data has been received.

By default, Intel recommends using the SDM_IO16 pin to implement the CONF_DONE function. If SDM_IO16 is unavailable, the CONF_DONE function can also be implemented using any unused SDM_IO pins. Except for SDM_IO0 and SDM_IO16, other SDM_IO pins are required to connect to an external 4.7 kΩ pull-down resistor for the CONF_DONE signal. Connect the CONF_DONE pin to the external configuration controller when configuring using the Avalon® streaming interface (AVST).

You have an option to monitor this signal with an external component if you are using the active serial (AS) x4 configuration scheme

SDM_IO0

SDM_IO10

SDM_IO11

SDM_IO12

SDM_IO13

SDM_IO14

SDM_IO16

PIN_PERST_N_CVP_L1[A, B, C, D]_[0, 1]

Input External reset signal pins for GTS transceiver in one PCIe* case.

Reset input in PCIe* case.

In a PCIe* adapter card implementation, connect this signal from the PCIe* edge connector to each GTS PCIe* reset input pin. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.

If the pin is assigned to PIN_PERST in Quartus IP but GTS is unused, tie it to GND.

In case one reset pin controls multiple PCIe* IPs in bifurcation mode, ensure that this signal is de-asserted high after all IPs reference clocks are stable.

If the I/O bank for PIN_PERST is powered at 1.8 V or 2.5 V, use a level translator to fan out and change the 3.3 V opendrain nPERST signal from the PCIe* connector to the 1.8 V or 2.5 V PIN_PERST input of each GTS PCIe* that is used on the board.

Provide a 1.8 V or 2.5 V pull-up resistor to the PIN_PERST input as the nPERST signal from the PCIe* connector is an opendrain signal. You must pull up the 3.3 V PCIe* nPERST signal on the adapter card.

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