Visible to Intel only — GUID: fhy1576610085843
Ixiasoft
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: fhy1576610085843
Ixiasoft
4.1.2.2. For CvP Update Mode
Before you perform CvP update mode, the device must be in user mode.
Note: For PCIe* 4.0 capable Endpoints, in user mode, Intel® recommends to verify that the link has been trained to the expected PCIe* 4.0 rate. If the link is not operating at PCIe* 4.0, software can trigger the Endpoint to retrain.