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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
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3.1. Single Endpoint
Use the single endpoint topology to configure a single FPGA. In this topology, the PCIe* link connects one PCIe* endpoint in the FPGA device to one PCIe* root port in the host.
Figure 3. Single Endpoint Topology