Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

ID 813775
Date 10/02/2024
Public

3.1. Single Endpoint

Use the single endpoint topology to configure a single FPGA. In this topology, the PCIe* link connects one PCIe* endpoint in the FPGA device to one PCIe* root port in the host.

Figure 3. Single Endpoint Topology