Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

ID 813775
Date 10/02/2024
Public

7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs

Document Version Changes
2024.10.02
  • Updated the label in PCIe* Timing Sequence in CvP Initialization Mode figure to FPGA Bottom Left or Top Left Transceiver Status.
  • Corrected recommended periphery image size limit to 12 Mb in the Configuration Images section.
  • Updated row C in the Power-Up Sequence Timing in CvP Initialization Mode table.
  • Updated the FPGA Power Supplies Ramp-Up Time and POR figure in the FPGA Power Supplies Ramp Time Requirement section.
2024.04.01 Initial release.