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1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
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1.3.1.1. CvP Error Recovery
In case of an error during CvP core configuration due to reasons like bitstream corruption, an incomplete bitstream, or an incompatible bitstream, you can retry the CvP update using a good bitstream to recover the error.