4.1.2.1. For CvP Initialization Mode
To meet the 120 ms wake-up time requirement for the PCIe* Hard IP in CvP initialization mode, you need to use periphery image because the configuration time for periphery image is significantly less than the full FPGA configuration time. You must use the Active Serial x4 (fast mode) configuration scheme for the periphery image configuration.
To ensure successful configuration, all POR-monitored power supplies must ramp up monotonically to the operating range within the 10 ms ramp-up time. The PERST# signal indicates when the FPGA power supplies are within their specified voltage tolerances and the REFCLK is stable2. The embedded hard reset controller triggers after the internal status signal indicates that the periphery image has been loaded. This reset does not trigger off of PERST#. For CvP Initialization mode, the PCIe* link supports the FPGA core image configuration and subsequent PCIe* applications in user mode.
Note: For PCIe* 4.0 capable Endpoints, after loading the core bitstream (core.rbf), Intel recommends to verify that the link has been trained to the expected PCIe* 4.0 rate. If the link is not operating at PCIe* 4.0, software can trigger the Endpoint to retrain.
Figure 6. PCIe* Timing Sequence in CvP Initialization Mode
| Timing Sequence | Timing Range (ms) | Description |
|---|---|---|
| a | 1.5–7.6 |
FPGA POR delay + bootup sequence until nstatus high (AS Fast Mode). |
| b | 80–100 |
Maximum time from the FPGA power up to the end of periphery configuration in CvP initialization mode (transceiver calibration start after reference clock is stable).
Note: During configuration, transceiver starts to perform calibration once out of reset and becomes active for link training. From power good to PCIe* link active, it has no dependency on the completion of periphery image configuration. The PCIe* Hard IP would enter link active state to meet 120ms before CONF_DONE asserted high.
|
| c | 0–20 | Minimum calibration time after PERST# is deasserted. |
| d | 100 | Minimum PERST# signal active from the host. |
| e | 120 | 120 ms of power stable to PCIe* link active time upon power up. |
| f | 100 | Maximum time PCIe* device must enter L0 after PERST# is deasserted.
Note: 100 ms timing range is only applicable to PCIe* PCIe* 1.0/ PCIe* 2.0. PCIe* 3.0 does not need to meet 100 ms timing requirement.
|
| g | 10 | Maximum ramp-up time requirement for all POR-monitored power supplies in the FPGA to reach their respective operating range |
| h | 70–90 | Periphery image loading time from nSTATUS to CONF_DONE. |
Note:
The periphery configuration time may vary depending on your configuration system setup and settings.
The following conditions were used to validate the power up sequence timing in CvP initialization mode:
- Set the VID mode of operation to PMBus Master mode3
- Use Intersil* ISL68137 regulator to regulate the PMBus
- Set configuration clock source to OSC_CLK_1 with 125 MHz
- No advanced security features were enabled
- For AS x4 configuration mode, set the AS_CLK to 166 MHz. Use a Micron* device with a 2 Gb density range QSPI flash memory.
2 REFCLK must be stable 100 µs before PERST# inactive in order to complete the link training.
3 VID mode is applicable to Agilex™ 5 devices with SmartVID enabled. It is not applicable for fixed voltage with SmartVID disabled.