Visible to Intel only — GUID: bmv1576617939148
Ixiasoft
Visible to Intel only — GUID: bmv1576617939148
Ixiasoft
2.2.1. CvP Initialization Mode
- Active Serial (AS) normal and fast modes
- AVST x8
- JTAG
To configure the periphery image while meeting the 120 ms of power stable to PCIe* link active time, you must specify the OSC_CLK_1 pin as 25 MHz, 100 MHz, or 125 MHz, and set the AS_CLK clock to 166 MHz.
After the periphery image configuration is complete, the CONF_DONE signal goes high and the FPGA starts PCIe* link training. When PCIe* link training is complete, the PCIe* link transitions to L0 state and then allows the host to complete PCIe* enumeration of the link. The PCIe* host then initiates the core image configuration through the PCIe* link.
After the core image configuration is complete, the CVP_CONFDONE pin (if enabled) goes high, indicating the FPGA is fully configured.
After the FPGA is fully configured, the FPGA enters user mode. If the INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is complete and the FPGA enters user mode.
In user mode, the PCIe* links are available for normal PCIe* applications.