Visible to Intel only — GUID: blh1576084154249
Ixiasoft
1. Overview
2. CvP Description
3. CvP Topologies
4. Design Considerations
5. CvP Driver and Registers
6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Agilex™ 5 FPGAs
7. Document Revision History for the Configuration via Protocol (CvP) Implementation User Guide: Agilex™ 5 FPGAs and SoCs
Visible to Intel only — GUID: blh1576084154249
Ixiasoft
2.3. Compression Features
Data Compression
The Quartus® Prime Pro Edition software compresses all Agilex™ 5 device bitstreams to reduce the storage requirement and increase bitstream processing speed. The periphery and core images are both compressed.