GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide

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ID 813754
Date 5/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Features 3. Getting Started with GTS AXI Streaming IP 4. IP Architecture and Functional Description 5. IP Parameters 6. Interfaces and Signals 7. Registers 8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide A. Troubleshooting/Debugging
1. Introduction x
1.1. About PCI Express* 1.2. Goal of the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide 1.3. Example Use Models
2. Features x
2.1. Supported Features 2.2. IP Support Status 2.3. Release Information 2.4. Recommended FPGA Fabric Speed Grades 2.5. Resource Utilization 2.6. IP Core and Design Example Support Levels
3. Getting Started with GTS AXI Streaming IP x
3.1. Downloading and Installing Quartus® Prime Software 3.2. Configuring and Generating the GTS AXI Streaming IP 3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP 3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP 3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs) 3.6. Simulating the GTS AXI Streaming IP Variant 3.7. Compiling the GTS AXI Streaming IP Variant
4. IP Architecture and Functional Description x
4.1. Clocking 4.2. Resets 4.3. PCIe* Hard IP 4.4. Hard IP Interface (IF) Adaptor 4.5. Interrupts 4.6. Transaction Ordering 4.7. TX Non-Posted Metering Requirement on Application 4.8. AXI4-Stream Interface 4.9. Tag Allocation 4.10. Precision Time Measurement (PTM) 4.11. Single Root I/O Virtualization (SR-IOV) 4.12. Transaction Layer Packet (TLP) Bypass Mode 4.13. Scalable IOV
4.1. Clocking x
4.1.1. Reference Clock
4.5. Interrupts x
4.5.1. Legacy Interrupt 4.5.2. Message Signaled Interrupts (MSI) 4.5.3. Message Signal Interrupt Extended (MSI-X)
4.8. AXI4-Stream Interface x
4.8.1. Header Format 4.8.2. Prefix Format 4.8.3. Function Number Format 4.8.4. BAR Number Format 4.8.5. Data and Header Packing Schemes 4.8.6. Simple Data and Header Packing Scheme
4.11. Single Root I/O Virtualization (SR-IOV) x
4.11.1. SR-IOV Implementation
4.12. Transaction Layer Packet (TLP) Bypass Mode x
4.12.1. AXI-Lite Usage for TLP Bypass Mode 4.12.2. Configuration TLP 4.12.3. Transmit Interface 4.12.4. Receive Interface 4.12.5. Malformed TLP 4.12.6. ECRC
5. IP Parameters x
5.1. PCIe* Interfaces 0 Settings 5.2. AXI Interfaces 0 Settings 5.3. PCIe* 0 Settings
5.3. PCIe* 0 Settings x
5.3.1. PCIe* 0 Axi Settings 5.3.2. PCIe* 0 Base Address Registers 5.3.3. PCIe* 0 Device Identification Registers 5.3.4. PCIe* 0 PCI Express* / PCI Capabilities
6. Interfaces and Signals x
6.1. Overview 6.2. Clocks and Resets 6.3. AXI4-Stream Interfaces 6.4. Configuration Intercept Interface 6.5. Control Shadow Interface 6.6. Transmit Flow Control Credit Interface 6.7. Completion Timeout Interface 6.8. Control and Status Register Responder Interface 6.9. Function Level Reset Interface 6.10. TLP Bypass Error Reporting Interface 6.11. VF Error Flag Interface 6.12. Precision Time Measurement (PTM) Interface 6.13. Serial Data Signals 6.14. Miscellaneous Signals
6.2. Clocks and Resets x
6.2.1. Interface Clock Signals 6.2.2. Interface Reset Signals
6.3. AXI4-Stream Interfaces x
6.3.1. AXI4-Stream Receive (RX) Interface 6.3.2. AXI4-Stream Transmit (TX) Interface
6.4. Configuration Intercept Interface x
6.4.1. Configuration Intercept Request Interface 6.4.2. Configuration Intercept Response Interface
6.9. Function Level Reset Interface x
6.9.1. Function Level Reset Received Interface 6.9.2. Function Level Reset Completion Interface
7. Registers x
7.1. Register Address Map 7.2. PCI Express* Configuration Space 7.3. HIP Port and Status Registers 7.4. Soft Register Address Map 7.5. Indirect Register Access 7.6. Virtual Function (VF) PCI Express* Configuration Space
7.2. PCI Express* Configuration Space x
7.2.1. PCI Express* Configuration Header Registers 7.2.2. PCI Express* Capability Structures 7.2.3. Physical Layer 16.0 GT/s Extended Capability Structures
7.2.2. PCI Express* Capability Structures x
7.2.2.1. MSI-X Registers
7.3. HIP Port and Status Registers x
7.3.1. Root Port Interrupt Registers 7.3.2. PTM Registers
7.3.1. Root Port Interrupt Registers x
7.3.1.1. Root Port Interrupt Status 7.3.1.2. Root Port IRQ Enable 7.3.1.3. Root Port Error Status 7.3.1.4. Root Port Error Status Enable
7.3.2. PTM Registers x
7.3.2.1. Time Adjustment (32-bit LSB) to PTM Local Clock 7.3.2.2. Time Adjustment (32-bit MSB) to PTM Local Clock 7.3.2.3. Error Status for PTM Requester Mode 7.3.2.4. PTM CTRL to HIP
7.4. Soft Register Address Map x
7.4.1. Control Registers 7.4.2. Debug Registers 7.4.3. Performance Monitor Registers
7.4.1. Control Registers x
7.4.1.1. GTS AXI Streaming IP Version 7.4.1.2. GTS AXI Streaming IP Features 7.4.1.3. GTS AXI Streaming IP Interface Attributes 7.4.1.4. LEGACY INTERRUPT CTRL 7.4.1.5. CFG REG IA CTRL 7.4.1.6. CFG REG IA FN NUM 7.4.1.7. CFG REG IA WRDATA 7.4.1.8. CFG REG IA RDDATA 7.4.1.9. PRS CTRL 7.4.1.10. MSI PENDING CTRL 7.4.1.11. MSI PENDING 7.4.1.12. D-STATE STS 7.4.1.13. CFG RETRY CTRL
7.4.2. Debug Registers x
7.4.2.1. HIP Status 7.4.2.2. HIP BP CYCLES 7.4.2.3. HIA BP CYCLES 7.4.2.4. APP BP CYCLES 7.4.2.5. HIA RX BP CYCLES
7.4.3. Performance Monitor Registers x
7.4.3.1. PERFMON CTRL 7.4.3.2. TX MRD TLP 7.4.3.3. TX MWR TLP 7.4.3.4. TX MSG TLP 7.4.3.5. TX CFGWR TLP 7.4.3.6. TX CFGRD TLP 7.4.3.7. RX MRD TLP 7.4.3.8. RX MWR TLP 7.4.3.9. RX MSG TLP 7.4.3.10. RX CFGWR TLP 7.4.3.11. RX CFGRD TLP 7.4.3.12. TX MEM DATA 7.4.3.13. TX CPL DATA 7.4.3.14. RX MEM DATA 7.4.3.15. RX CPL DATA
7.6. Virtual Function (VF) PCI Express* Configuration Space x
7.6.1. VF PCI-Compatible Configuration Space Header Type0 7.6.2. VF Message Signal Interrupt Extended (MSI-X) Capability Structure 7.6.3. VF PCI Express* Capability Structure 7.6.4. VF Alternative Routing ID (ARI) Capability Structure 7.6.5. VF Transaction Processing Hints (TPH) Capability Structure 7.6.6. VF Address Translation Services (ATS) Capability Structure 7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.1. VF PCI-Compatible Configuration Space Header Type0 x
7.6.1.1. Vendor ID and Device ID Registers 7.6.1.2. Command Registers 7.6.1.3. Status Registers 7.6.1.4. Revision ID and Class Code Register 7.6.1.5. BIST, Header Type, Latency Timer, and Cache Line Size Registers 7.6.1.6. Subsystem Vendor ID and Subsystem ID Register 7.6.1.7. Capabilities Pointer
7.6.2. VF Message Signal Interrupt Extended (MSI-X) Capability Structure x
7.6.2.1. MSI-X Control Register 7.6.2.2. MSI-X Table Offset Register 7.6.2.3. MSI-X Pending Bit Array Register
7.6.3. VF PCI Express* Capability Structure x
7.6.3.1. PCI Express* Capability List Register 7.6.3.2. PCI Express* Device Capabilities Register 7.6.3.3. PCI Express* Device Control and Status Register 7.6.3.4. Link Capabilities Register 7.6.3.5. Link Control and Status Register 7.6.3.6. PCI Express* Device Capabilities 2 Register 7.6.3.7. PCI Express* Device Control and Status 2 Register 7.6.3.8. Link Capabilities 2 Register 7.6.3.9. Link Control and Status 2 Register
7.6.4. VF Alternative Routing ID (ARI) Capability Structure x
7.6.4.1. ARI Enhanced Capability Header Register 7.6.4.2. ARI Capability and Control Registers
7.6.5. VF Transaction Processing Hints (TPH) Capability Structure x
7.6.5.1. TPH Requester Enhanced Capability Header 7.6.5.2. TPH Requester Capability Register 7.6.5.3. TPH Requester Control Register
7.6.6. VF Address Translation Services (ATS) Capability Structure x
7.6.6.1. ATS Enhanced Capability Header 7.6.6.2. ATS Capability Register and Control Register
7.6.7. VF Access Control Services (ACS) Capability Structure x
7.6.7.1. ACS Extended Capability Header 7.6.7.2. ACS Capability and Control Register 7.6.7.3. Egress Control Vector
A. Troubleshooting/Debugging x
A.1. Hardware A.2. Debug Toolkit
A.1. Hardware x
A.1.1. Debugging Link Training Issues A.1.2. Debugging Data Transfer and Performance Issues
A.1.1. Debugging Link Training Issues x
A.1.1.1. Generic Tools and Utilities A.1.1.2. Signal Tap Logic Analyzer
A.2. Debug Toolkit x
A.2.1. Overview A.2.2. Enabling the Agilex™ 5 Debug Toolkit A.2.3. Launching the Agilex™ 5 Debug Toolkit A.2.4. Using the Agilex™ 5 Debug Toolkit A.2.5. Using the Agilex™ 5 Link Inspector
A.2.4. Using the Agilex™ 5 Debug Toolkit x
A.2.4.1. Main View A.2.4.2. Toolkit Parameters A.2.4.3. Channel Parameters A.2.4.4. Eye Viewer
A.2.4.2. Toolkit Parameters x
A.2.4.2.1. Agilex™ 5 Information A.2.4.2.2. Event Counter A.2.4.2.3. P0 Configuration Space
A.2.4.3. Channel Parameters x
A.2.4.3.1. General PHY A.2.4.3.2. TX Path A.2.4.3.3. RX Path
1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging

4.12.1. AXI-Lite Usage for TLP Bypass Mode

The majority of the PCIe* standard registers are implemented in the user’s logic outside of the GTS AXI Streaming IP. However, the following registers remain inside the Agilex™ 5 PCIe* Hard IP:
  • Power management capability
  • PCI Express* capability
  • Secondary PCI Express* capability
  • Data link feature extended capability
  • Physical layer 16.0 GT/s extended capability
  • Lane margining at the receiver extended capability
  • Advanced error reporting capability

The application can only access PCIe* controller registers through the AXI-Lite interface.

Table 22.  Capability Registers to be updated by the Application Logic via the Control and Status Register Responder Interface
Capability Description
Power Management Capability Needed to write back for triggering a PCI-PM entry.
PCI Express Capability

All the PCIe* capabilities, control, and status registers are for configuring the device.

Write-back is required.
Secondary PCI Express Capability Secondary PCIe* Capability is required for configuring the device.
Data Link Feature Extended Capability Data Link Capability is device specific.
Physical Layer 16.0 GT/s Extended Capability Physical Layer 16G Capability is device specific.
Lane Margining at the Receiver Extended Capability Margining Extended Capability is device specific.
Advanced Error Reporting Capability Write-back to error status registers is required for TLP Bypass.
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