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1. Introduction
2. Features
3. Getting Started with GTS AXI Streaming IP
4. IP Architecture and Functional Description
5. IP Parameters
6. Interfaces and Signals
7. Registers
8. Document Revision History for the GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A. Troubleshooting/Debugging
3.1. Downloading and Installing Quartus® Prime Software
3.2. Configuring and Generating the GTS AXI Streaming IP
3.3. Configuring and Generating GTS System PLL Clocks Intel® FPGA IP
3.4. Configuring and Generating GTS Reset Sequencer Intel® FPGA IP
3.5. Instantiating and Connecting GTS AXI Streaming IP Interfaces (and Other IPs)
3.6. Simulating the GTS AXI Streaming IP Variant
3.7. Compiling the GTS AXI Streaming IP Variant
4.1. Clocking
4.2. Resets
4.3. PCIe* Hard IP
4.4. Hard IP Interface (IF) Adaptor
4.5. Interrupts
4.6. Transaction Ordering
4.7. TX Non-Posted Metering Requirement on Application
4.8. AXI4-Stream Interface
4.9. Tag Allocation
4.10. Precision Time Measurement (PTM)
4.11. Single Root I/O Virtualization (SR-IOV)
4.12. Transaction Layer Packet (TLP) Bypass Mode
4.13. Scalable IOV
6.1. Overview
6.2. Clocks and Resets
6.3. AXI4-Stream Interfaces
6.4. Configuration Intercept Interface
6.5. Control Shadow Interface
6.6. Transmit Flow Control Credit Interface
6.7. Completion Timeout Interface
6.8. Control and Status Register Responder Interface
6.9. Function Level Reset Interface
6.10. TLP Bypass Error Reporting Interface
6.11. VF Error Flag Interface
6.12. Precision Time Measurement (PTM) Interface
6.13. Serial Data Signals
6.14. Miscellaneous Signals
7.4.1.1. GTS AXI Streaming IP Version
7.4.1.2. GTS AXI Streaming IP Features
7.4.1.3. GTS AXI Streaming IP Interface Attributes
7.4.1.4. LEGACY INTERRUPT CTRL
7.4.1.5. CFG REG IA CTRL
7.4.1.6. CFG REG IA FN NUM
7.4.1.7. CFG REG IA WRDATA
7.4.1.8. CFG REG IA RDDATA
7.4.1.9. PRS CTRL
7.4.1.10. MSI PENDING CTRL
7.4.1.11. MSI PENDING
7.4.1.12. D-STATE STS
7.4.1.13. CFG RETRY CTRL
7.4.3.1. PERFMON CTRL
7.4.3.2. TX MRD TLP
7.4.3.3. TX MWR TLP
7.4.3.4. TX MSG TLP
7.4.3.5. TX CFGWR TLP
7.4.3.6. TX CFGRD TLP
7.4.3.7. RX MRD TLP
7.4.3.8. RX MWR TLP
7.4.3.9. RX MSG TLP
7.4.3.10. RX CFGWR TLP
7.4.3.11. RX CFGRD TLP
7.4.3.12. TX MEM DATA
7.4.3.13. TX CPL DATA
7.4.3.14. RX MEM DATA
7.4.3.15. RX CPL DATA
7.6.1. VF PCI-Compatible Configuration Space Header Type0
7.6.2. VF Message Signal Interrupt Extended (MSI-X) Capability Structure
7.6.3. VF PCI Express* Capability Structure
7.6.4. VF Alternative Routing ID (ARI) Capability Structure
7.6.5. VF Transaction Processing Hints (TPH) Capability Structure
7.6.6. VF Address Translation Services (ATS) Capability Structure
7.6.7. VF Access Control Services (ACS) Capability Structure
7.6.3.1. PCI Express* Capability List Register
7.6.3.2. PCI Express* Device Capabilities Register
7.6.3.3. PCI Express* Device Control and Status Register
7.6.3.4. Link Capabilities Register
7.6.3.5. Link Control and Status Register
7.6.3.6. PCI Express* Device Capabilities 2 Register
7.6.3.7. PCI Express* Device Control and Status 2 Register
7.6.3.8. Link Capabilities 2 Register
7.6.3.9. Link Control and Status 2 Register
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7.1. Register Address Map
User application logic can access registers of the GTS AXI Streaming IP as well as HIP physical function (PF) configuration space registers through the AXI4-Lite Control and Status Register Responder interface. The offsets are provided in the following table. The following sections describe the details on the register addresses and bit mappings for each register space.
Offset | Registers |
---|---|
0x8_3000 – 0x8_3FFF | PF3 PCIe* Configuration Space |
0x8_2000 – 0x8_2FFF | PF2 PCIe* Configuration Space |
0x8_1000 – 0x8_1FFF | PF1 PCIe* Configuration Space |
0x8_0000 – 0x8_0FFF | PF0 PCIe* Configuration Space |
0x1_414C – 0x1_415B | Root Port Interrupt Status Registers |
0x1_41A0 – 0x1_41AF | PTM Register |
0x0_0800 – 0x0_0BFF | Performance Monitor Registers |
0x0_0400 – 0x0_07FF | Debug Registers |
0x0_0000 – 0x0_03FF | Control Registers |
All AXI-Lite accesses are completed with appropriate response (BRESP, RRESP) so that the bus does not stall.
- AXI-Lite access to address ranges defined in the Register Address Map must be completed successfully with BRESP/RRESP="OK". This includes access to unimplemented, i.e., Reserved, register offsets within the valid address range.
- Read to reserved register returns value of all zeroes.
- Write to register location containing any number of the RO or RO/V bit, the design returns write response BRESP=OKAY. Write is dropped for the RO or RO/V bit location(s). This is not an error condition.
- AXI-Lite access to address beyond the register map must be completed gracefully with BRESP/RRESP="DECERR". Read returns all zeroes and write is dropped.