GTS AXI Streaming Intel® FPGA IP for PCI Express* User Guide
A newer version of this document is available. Customers should click here to go to the newest version.
Visible to Intel only — GUID: atc1711419021264
Ixiasoft
Visible to Intel only — GUID: atc1711419021264
Ixiasoft
6.9.1. Function Level Reset Received Interface
Signal Name | Direction | Endpoint (EP)/Root Port (RP)/TLP Bypass (BP) | Clock Domain | Description |
---|---|---|---|---|
p0_ss_app_st_flrrcvd_tvalid | Output | EP | coreclkout_hip | When asserted, indicates a FLR request received from HOST. The signal is valid for one clock cycle. |
p0_ss_app_st_flrrcvd_tdata[19:0] | Output | EP | coreclkout_hip | Valid when flrcmpl_tvalid assert.
|
The figure below shows timing diagram for function level reset indication to the application.
The first command indicates FLR for Physical Function = 1 on slot = 0.
The second and third back-to-back indications are for VF, the ss_app_st_flrrcvd_tdata[14] high indicates FLR is received for Virtual Function.
The fourth command signals FLR for PF=0.