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Ixiasoft
1.4.1. Simulation Design Example Components
The simulation design example top-level test file is basic_avl_tb_top.sv. This file provides a clock reference clk_ref_p of 156.25 MHz to the PHY. It includes a task to send and receive 10 packets.
File Names |
Description |
---|---|
Key Testbench and Simulation Files |
|
basic_avl_tb_top.v | Top-level testbench file. The testbench instantiates the DUT and runs Verilog HDL tasks to generate and accept packets. |
Testbench Scripts |
|
run_vsim.do | The Siemens* EDA QuestaSim* script to run the testbench. |
run_vcs.sh | The Synopsys* VCS* script to run the testbench. |
run_vcsmx.sh | The Synopsys* VCS* MX script (combined Verilog HDL and SystemVerilog with VHDL) to run the testbench. |
run_xcelium.sh | The Cadence* Xcelium* script to run the testbench. |