Low Latency 40G Ethernet Intel® FPGA IP Design Example User Guide: Agilex™ 5 FPGAs and SoCs

ID 813654
Date 8/16/2024
Public

2.1. Features

  • Supports transmit (TX) cyclic redundancy check (CRC) insertion and media access controller (MAC) flow control
  • Supports preamble pass-through and link training.
  • Generates design example with MAC stats counters feature.
  • Provides testbench and simulation script.