AXI Streaming Intel® FPGA IP for PCI Express* User Guide
Visible to Intel only — GUID: wsz1700067284851
Ixiasoft
Visible to Intel only — GUID: wsz1700067284851
Ixiasoft
6.5. Configuration Intercept Interface
The IP allows application logic to intercept configuration read and configuration write requests using this interface. The interface follows AXI Streaming interface protocol with ready valid handshake. The interface will support a maximum of one outstanding request at a time. The IP provides st_ciireq and st_ciiresp interfaces for intercepting packets.
- This interface is provided so that the PCIe* IP is backward compatible to legacy application logic that relies on CII for their functionality. Newly defined application logic should avoid using the CII interface and move to the CEB interface.
- This interface is mutually exclusive with the Configuration Extension Bus Request Interface.
This interface is applicable only when operating in Endpoint mode.