Visible to Intel only — GUID: lpk1700067362100
Ixiasoft
Visible to Intel only — GUID: lpk1700067362100
Ixiasoft
6.14. Serial Data Signals
The AXI Streaming Intel® FPGA IP for PCI Express* for PCI Express* natively supports 4, 8, or 16 PCIe* lanes. Each lane includes a TX differential pair and an RX differential pair. Data is striped across all available lanes. Refer to the table Variables Used in the Bus Indices for more details on bus indices.
The following table shows the signals of the Serial Interface of the AXI Streaming Intel® FPGA IP for PCI Express* .
Signal Name | Direction | Clock Domain | Description |
---|---|---|---|
tx_p_out[<b>-1:0], tx_n_out[<b>-1:0] |
Output | N/A | Transmit serial data outputs using the High-Speed Differential I/O standard. |
rx_p_in[<b>-1:0], rx_n_in[<b>-1:0] |
Input | N/A | Receive serial data inputs using the High-Speed Differential I/O standard. |