External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

ID 772632
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.1.1.1. Memory Device Description IP Parameter Editor Guidelines

This topic provides high-level guidance for parameterizing the tabs in the Intel Agilex® 7 EMIF Memory Device Description IP parameter editor.
Table 1.  EMIF Parameter Editor Guidelines
Parameter Editor Tab Guidelines
High Level Parameters Ensure that you enter the following parameters correctly:
  • Memory format: Specifies the packaging of the memory device.
  • Enable Data Mask: Specifies whether byte masking is to be enabled by the memory.
  • Density of each memory component: Specifies the density of each memory component in Gbits.
Memory Interface Parameters Select the required parameters for the following:
  • Data bus settings.
Memory Timing Parameters Allows you to modify the frequency and timing settings for the device.

For detailed information on individual parameters, refer to the appropriate protocol-specific chapter in the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide.

Figure 6. EMIF Memory Device Description Parameter Editor