External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

Download PDF
ID 772632
Date 12/04/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP 4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
1.1. Release Information
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
2.1. Creating an EMIF Project 2.2. Generating and Configuring the EMIF IP 2.3. Configuring DQ Pin Swizzling 2.4. Generating the Synthesizable EMIF Design Example 2.5. Generating the EMIF Design Example for Simulation 2.6. Pin Placement for Intel Agilex® 7 M-Series EMIF IP 2.7. Compiling the Intel Agilex® 7 M-Series EMIF Design Example 2.8. Generating the EMIF Design Example with the Performance Monitor
2.1. Creating an EMIF Project x
2.1.1. Generating a Custom Memory Presets File
2.1.1. Generating a Custom Memory Presets File x
2.1.1.1. Memory Device Description IP Parameter Editor Guidelines 2.1.1.2. Saving a Memory Device Presets File 2.1.1.3. Examples for Generating a Custom Memory Presets File
2.1.1.3. Examples for Generating a Custom Memory Presets File x
2.1.1.3.1. Generating a Custom Memory Preset File for DDR4 2.1.1.3.2. Guidelines for Selecting the DDR4 DRAM Component Package Type 2.1.1.3.3. Generating a Custom Memory Preset File for DDR5 2.1.1.3.4. Guidelines for Selecting the DDR5 DRAM Component Package Type 2.1.1.3.5. Generating a Custom Memory Preset File for LPDDR5
2.2. Generating and Configuring the EMIF IP x
2.2.1. Intel Agilex® 7 M-Series EMIF Parameter Editor Guidelines 2.2.2. Using Custom Memory Device Presets from a File
2.3. Configuring DQ Pin Swizzling x
2.3.1. Example: DQ Pin Swizzling Within DQS group for x32 DDR4 interface 2.3.2. Example: Byte Swizzling for a x32 DDR4 interface, using a memory device of x8 width 2.3.3. Combining Pin and Byte Swizzling 2.3.4. Example: Swizzling for a x32 + ECC interface 2.3.5. Example: Byte Swizzling for Lockstep Configuration
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP x
3.1. Synthesis Design Example 3.2. Simulation Design Example 3.3. Example Design Tab
3.2. Simulation Design Example x
3.2.1. Running Simulation
1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Design Example Quick Start Guide for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
3. Design Example Description for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
4. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP Design Example User Guide

2.1.1.3.5. Generating a Custom Memory Preset File for LPDDR5

To generate a custom preset file for LPDDR5, follow these steps:

  1. In the IP Catalog, select Memory Device Description IP (LPDDR5).
    Figure 15. IP Catalog
  2. Type a name for the IP instance and click Create.
    Figure 16. Creating a New IP Instance
  3. Refer to the following figures for the steps in creating and saving the custom presets file:
    Figure 17. Parameterizing EMIF Memory Device Description IP (LPDDR5) – Part 1
    Figure 18. Parameterizing EMIF Memory Device Description IP (LPDDR5) – Part 2
Level Two Title