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1. About the External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP
2. Intel Agilex® 7 M-Series FPGA EMIF IP – Introduction
3. Intel Agilex® 7 M-Series FPGA EMIF IP – Product Architecture
4. Intel Agilex® 7 M-Series FPGA EMIF IP – End-User Signals
5. Intel Agilex® 7 M-Series FPGA EMIF IP – Simulating Memory IP
6. Intel Agilex 7 M-Series FPGA EMIF IP – DDR4 Support
7. Intel Agilex® 7 M-Series FPGA EMIF IP – DDR5 Support
8. Intel Agilex 7 M-Series FPGA EMIF IP – LPDDR5 Support
9. Intel Agilex® 7 M-Series FPGA EMIF IP – Timing Closure
10. Intel Agilex® 7 M-Series FPGA EMIF IP – Controller Optimization
11. Intel Agilex® 7 M-Series FPGA EMIF IP – Debugging
12. Document Revision History for External Memory Interfaces Intel Agilex® 7 M-Series FPGA IP User Guide
3.1.1. Intel Agilex® 7 M-Series EMIF Architecture: I/O Subsystem
3.1.2. Intel Agilex® 7 M-Series EMIF Architecture: I/O SSM
3.1.3. Intel Agilex® 7 M-Series EMIF Architecture: I/O Bank
3.1.4. Intel Agilex® 7 M-Series EMIF Architecture: I/O Lane
3.1.5. Intel Agilex® 7 M-Series EMIF Architecture: Input DQS Clock Tree
3.1.6. Intel Agilex® 7 M-Series EMIF Architecture: PHY Clock Tree
3.1.7. Intel Agilex® 7 M-Series EMIF Architecture: PLL Reference Clock Networks
3.1.8. Intel Agilex® 7 M-Series EMIF Architecture: Clock Phase Alignment
6.2.4.1. Address and Command Pin Placement for DDR4
6.2.4.2. DDR4 Data Width Mapping
6.2.4.3. General Guidelines
6.2.4.4. x4 DIMM Implementation
6.2.4.5. Specific Pin Connection Requirements
6.2.4.6. Command and Address Signals
6.2.4.7. Clock Signals
6.2.4.8. Data, Data Strobes, DM/DBI, and Optional ECC Signals
6.3.5.1. Single Rank x 8 Discrete (Component) Topology
6.3.5.2. Single Rank x 16 Discrete (Component) Topology
6.3.5.3. ADDR/CMD Reference Voltage/RESET Signal Routing Guidelines for Single Rank x 8 and Single Rank x 16 Discrete (Component) Topologies
6.3.5.4. Skew Matching Guidelines for DDR4 Discrete Configurations
6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
6.3.5.6. Intel Agilex® 7 M-Series EMIF Pin Swapping Guidelines
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6.3.5.5. Power Delivery Recommendations for DDR4 Discrete Configurations
This topic describes power distribution network (PDN) design guidelines for the memory side in discrete topologies.
Note: For information on power distribution network design at the FPGA to meet timing margins, refer to the Intel Agilex® 7 M-Series PDN design guidelines.
In the following table, the number of decoupling capacitors is based on a single channel. If multiple channels are sharing the same power rail, the number of decoupling capacitors at the memories must be scaled accordingly for all channels.
Physically small decoupling capacitors are recommended to minimize area, inductance, and resistance on the PDN path on the printed circuit board.
Memory Configuration | Power Domain | Decoupling Location | Quantity × Value (size) |
---|---|---|---|
Discrete (Component) Single Rank x8 | VDDQ/VDD shorted | 4 near each x8 DRAM device | 36 x 1uF (0402) |
Distribute around DRAM devices | 9 x 10uF (0603) | ||
VPP | 2 near each x8 DRAM device | 18 x 1uF (0402) | |
Distribute around DRAM devices | 5 x 10uF (0603) | ||
VTT | Place near Rtt (termination resistors) | 16 x 1uF (0402) | |
Place near Rtt (termination resistors) | 4 x 10uF (0603) | ||
Discrete (Component) Single Rank x16 | VDDQ/VDD shorted | 4 near each x16 DRAM device | 18 x 1uF (0402) |
Distribute around DRAM devices | 5 x 10uF (0603) | ||
VPP | 2 near each x16 DRAM device | 10 x 1uF (0402) | |
Distribute around DRAM devices | 3 x 10uF (0603) | ||
VTT | Place near Rtt (termination resistors) | 8 x 1uF (0402) | |
Place near Rtt (termination resistors) | 2 x 10uF (0603) |