Parameterizable Macros for Intel® FPGAs User Guide

ID 772350
Date 7/08/2024
Public
Document Table of Contents

5.2.4. Asynchronous Reset Synchronizer Verilog Instantiation Template

Asynchronous Reset Synchronizer Verilog Instantiation Template

//Quartus Prime Parameterizable Macro Template
//  IPM_CDC_ASYNC_RST
//Documentation :
//https://www.intel.com/content/www/us/en/docs/programmable/772350/
//Macro Location :
//$QUARTUS_ROOTDIR/libraries/megafunctions/ipm_cdc_async_rst.sv
	
 ipm_cdc_async_rst #(
   .RST_TYPE                   ("ACTIVE_HIGH"),
   .NUM_STAGES                 (3)
	 ) <instance_name> (
     .clk       (_connected_to_clk_),        //input, width = 1
     .arst_in   (_connected_to_arst_in_),    //input, width = 1
     .srst_out  (_connected_to_srst_out_)    //output, width = 1
	);