Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

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ID 772138
Date 9/11/2023
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Document Table of Contents
Document Table of Contents x
1. Intel Agilex® 7 M-Series General-Purpose I/O Overview 2. Intel Agilex® 7 M-Series GPIO-B Banks 3. Intel Agilex® 7 M-Series HPS I/O Banks 4. Intel Agilex® 7 M-Series SDM I/O Banks 5. Intel Agilex® 7 M-Series I/O Troubleshooting Guidelines 6. GPIO Intel® FPGA IP 7. Programmable I/O Features Description 8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series 9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series
1. Intel Agilex® 7 M-Series General-Purpose I/O Overview x
1.1. Package Selection and I/O Vertical Migration Support 1.2. Types of I/O Banks
2. Intel Agilex® 7 M-Series GPIO-B Banks x
2.1. GPIO-B Bank Overview 2.2. GPIO-B Features 2.3. GPIO-B Implementation Guide 2.4. GPIO-B Termination 2.5. GPIO-B Design Guidelines 2.6. GPIO-B Simulation
2.1. GPIO-B Bank Overview x
2.1.1. GPIO-B Bank Structure 2.1.2. GPIO-B Buffers and Registers
2.2. GPIO-B Features x
2.2.1. Supported I/O Standards for GPIO-B Banks 2.2.2. GPIO-B Buffer Behavior 2.2.3. Programmable I/O Element Features for the GPIO-B Bank
2.2.3. Programmable I/O Element Features for the GPIO-B Bank x
2.2.3.1. Guidelines: Programmable Output Slew Rate Control 2.2.3.2. Guidelines: Programmable Pull-Up Resistor 2.2.3.3. Guidelines: Programmable De-Emphasis 2.2.3.4. Guidelines: Programmable Receiver Equalization Calibration
2.3. GPIO-B Implementation Guide x
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 2.3.2. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
2.3.1. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
2.3.1.1. Assigning Pin I/O Standards in the Intel® Quartus® Prime Assignment Editor 2.3.1.2. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 2.3.1.3. GPIO-B Programmable IOE Features Assignment Names and Settings
2.4. GPIO-B Termination x
2.4.1. Single-Ended I/O Termination in M-Series Devices 2.4.2. True Differential Signaling I/O Termination
2.4.1. Single-Ended I/O Termination in M-Series Devices x
2.4.1.1. Single-Ended I/O Standard OCT Termination 2.4.1.2. OCT Calibration Block 2.4.1.3. Single-Ended I/O Standards External Termination 2.4.1.4. Single-Ended I/O Termination Implementation Guide
2.4.1.1. Single-Ended I/O Standard OCT Termination x
2.4.1.1.1. RS OCT 2.4.1.1.2. RT OCT 2.4.1.1.3. Dynamic OCT
2.4.1.4. Single-Ended I/O Termination Implementation Guide x
2.4.1.4.1. Configuring OCT Using the Assignment Editor 2.4.1.4.2. OCT Features Assignment Names and Settings
2.4.2. True Differential Signaling I/O Termination x
2.4.2.1. True Differential Signaling I/O Standard OCT Termination 2.4.2.2. True Differential Signaling I/O Standard External Termination
2.4.2.1. True Differential Signaling I/O Standard OCT Termination x
2.4.2.1.1. Configuring Differential Input RD OCT Using the Assignment Editor 2.4.2.1.2. Guidelines: Differential Input RD OCT
2.5. GPIO-B Design Guidelines x
2.5.1. I/O Standard Placement Restrictions for True Differential I/Os 2.5.2. Placement Restrictions for True Differential and Single-Ended I/O Standards in the Same or Adjacent GPIO-B Bank 2.5.3. VREF Sources and Input Standards Grouping 2.5.4. GPIO-B Pin Restrictions for External Memory Interfaces 2.5.5. RZQ Pin Requirement 2.5.6. I/O Standards Implementation Based on VCCIO_PIO Voltages 2.5.7. I/O Standard Selection and I/O Bank Supply Compatibility Check 2.5.8. Simultaneous Switching Noise 2.5.9. HPS Shared I/O Requirements 2.5.10. Clocking Requirements 2.5.11. SDM Shared I/O Requirements 2.5.12. Unused Pins 2.5.13. VCCIO_PIO Supply for Unused GPIO-B Banks 2.5.14. GPIO-B Pins During Power Sequencing 2.5.15. Drive Strength Requirement for GPIO-B Input Pins 2.5.16. Maximum DC Current Restrictions 2.5.17. 1.05 V, 1.1 V, or 1.2 V I/O Interface Voltage Level Compatibility 2.5.18. Connection to True Differential Signaling Input Buffers During Device Reconfiguration 2.5.19. LVSTL700 I/O Standards Differential Pin Pair Requirements 2.5.20. Implementing a Pseudo Open Drain 2.5.21. Allowed Duration for Using RT OCT 2.5.22. Single-Ended Strobe Signal Differential Pin Pair Restriction
2.6. GPIO-B Simulation x
2.6.1. IBIS Models 2.6.2. IBIS-AMI Models 2.6.3. HSPICE* Models 2.6.4. Net Length Reports
3. Intel Agilex® 7 M-Series HPS I/O Banks x
3.1. HPS I/O Bank Overview 3.2. HPS I/O Features 3.3. HPS I/O Implementation Guide 3.4. HPS I/O Design Guidelines 3.5. HPS I/O Simulation
3.2. HPS I/O Features x
3.2.1. Supported I/O Standards for HPS I/O Banks 3.2.2. Programmable I/O Element Features for the HPS I/O Bank 3.2.3. HPS I/O Buffer Behavior
3.3. HPS I/O Implementation Guide x
3.3.1. Configuring Open Drain Feature for the HPS I/O 3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor 3.3.3. Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner
3.3.2. I/O Assignments with the Intel® Quartus® Prime Assignment Editor x
3.3.2.1. Assigning Programmable IOE Features in the Intel® Quartus® Prime Assignment Editor 3.3.2.2. HPS I/O Programmable IOE Features Assignment Names and Settings
3.4. HPS I/O Design Guidelines x
3.4.1. HPS I/O Pins During Power Sequencing 3.4.2. HPS Shared I/O Requirements
3.5. HPS I/O Simulation x
3.5.1. HPS IBIS Models 3.5.2. Net Length Reports
4. Intel Agilex® 7 M-Series SDM I/O Banks x
4.1. SDM I/O Bank Overview 4.2. SDM I/O Features 4.3. SDM I/O Design Guidelines 4.4. SDM I/O Simulation
4.2. SDM I/O Features x
4.2.1. Supported I/O Standards for SDM I/O Banks 4.2.2. SDM I/O Buffer Behavior 4.2.3. I/O Standards and Features for Configuration Pins
4.3. SDM I/O Design Guidelines x
4.3.1. SDM I/O Pins During Power Sequencing 4.3.2. Avalon® Streaming Interface Dedicated Configuration Pins
4.4. SDM I/O Simulation x
4.4.1. SDM IBIS Models 4.4.2. Net Length Reports
6. GPIO Intel® FPGA IP x
6.1. Release Information for GPIO Intel® FPGA IP 6.2. Generating the GPIO Intel® FPGA IP 6.3. GPIO Intel® FPGA IP Parameter Settings 6.4. GPIO Intel® FPGA IP Interface Signals 6.5. GPIO Intel® FPGA IP Architecture 6.6. Verifying Resource Utilization and Design Performance 6.7. GPIO Intel® FPGA IP Timing 6.8. GPIO Intel® FPGA IP Design Examples
6.2. Generating the GPIO Intel® FPGA IP x
6.2.1. Intel® FPGA IP Generation Output
6.3. GPIO Intel® FPGA IP Parameter Settings x
6.3.1. Guideline: Swap datain_h and datain_l Ports in Migrated IP
6.4. GPIO Intel® FPGA IP Interface Signals x
6.4.1. Shared Signals 6.4.2. Data Bit-Order for Data Interface 6.4.3. Input and Output Bus High and Low Bits 6.4.4. Data Interface Signals and Corresponding Clocks
6.5. GPIO Intel® FPGA IP Architecture x
6.5.1. GPIO Intel® FPGA IP Data Paths 6.5.2. Register Packing
6.5.1. GPIO Intel® FPGA IP Data Paths x
6.5.1.1. Input Path 6.5.1.2. Output and Output Enable Paths
6.7. GPIO Intel® FPGA IP Timing x
6.7.1. Timing Components 6.7.2. Delay Elements 6.7.3. Timing Analysis 6.7.4. Timing Closure Guidelines
6.7.3. Timing Analysis x
6.7.3.1. Single Data Rate Input Register 6.7.3.2. DDIO Input Register 6.7.3.3. Single Data Rate Output Register 6.7.3.4. DDIO Output Register
6.8. GPIO Intel® FPGA IP Design Examples x
6.8.1. GPIO Intel® FPGA IP Synthesizable Intel® Quartus® Prime Design Example 6.8.2. GPIO Intel® FPGA IP Simulation Design Example
7. Programmable I/O Features Description x
7.1. Programmable Pre-Emphasis 7.2. Programmable De-Emphasis 7.3. Programmable Differential Output Voltage 7.4. Continuous Time Linear Equalization 7.5. Decision Feedback Equalization
1. Intel Agilex® 7 M-Series General-Purpose I/O Overview
2. Intel Agilex® 7 M-Series GPIO-B Banks
3. Intel Agilex® 7 M-Series HPS I/O Banks
4. Intel Agilex® 7 M-Series SDM I/O Banks
5. Intel Agilex® 7 M-Series I/O Troubleshooting Guidelines
6. GPIO Intel® FPGA IP
7. Programmable I/O Features Description
8. Documentation Related to the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series
9. Document Revision History for the Intel Agilex® 7 General-Purpose I/O User Guide: M-Series

4.2.3. I/O Standards and Features for Configuration Pins

The SDM pins have different I/O standards and features in different configuration schemes. You can assign the unused SDM pins for other functions in the Intel® Quartus® Prime software.
Table 35.   Intel Agilex® 7 AS ×4 Configuration Scheme—Dedicated Configuration Pins
Pin Function SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down Drive Strength Open Drain Slew Rate
AS_DATA1 SDM_IO1 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_CLK SDM_IO2 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AS_DATA2 SDM_IO3 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_DATA0 SDM_IO4 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_nCSO0 SDM_IO5 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AS_DATA3 SDM_IO6 Bidirectional 1.8 V LVCMOS Schmitt Trigger Disable 8 mA Disable Fast
AS_nCSO2 SDM_IO7 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AS_nCSO3 SDM_IO8 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AS_nCSO1 SDM_IO9 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AS_nRST SDM_IO15 Output 1.8 V LVCMOS — — 8 mA Disable Fast
Table 36.   Intel Agilex® 7 AS ×4 Configuration Scheme—Unused Configuration PinsFor the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.
SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down
SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
SDM_IO10 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO11 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO13 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO14 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
Table 37.   Intel Agilex® 7 Avalon® Streaming Interface ×8 Configuration Scheme—Dedicated Configuration Pins
Pin Function SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down Drive Strength Open Drain Slew Rate
AVSTx8_DATA2 SDM_IO1 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_DATA0 SDM_IO2 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_DATA3 SDM_IO3 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_DATA1 SDM_IO4 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_DATA4 SDM_IO6 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_READY SDM_IO8 Output 1.8 V LVCMOS — — 8 mA Disable Fast
AVSTx8_DATA7 SDM_IO10 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_VALID SDM_IO11 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor — — —
AVSTx8_DATA5 SDM_IO13 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_CLK SDM_IO14 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
AVSTx8_DATA6 SDM_IO15 Input 1.8 V LVCMOS Schmitt Trigger Disable — — —
Table 38.   Intel Agilex® 7 Avalon® Streaming Interface ×8 Configuration Scheme—Unused Configuration PinsFor the unused configuration pins, the drive strength, open drain, and slew rate settings are not applicable.
SDM I/O Direction I/O Standard Schmitt Trigger/TTL Input Weak Pull-Up/Pull-Down
SDM_IO0 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
SDM_IO5 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO7 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO9 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO12 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor
SDM_IO16 Input 1.8 V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor
Table 39.   Intel Agilex® 7 Avalon® Streaming Interface ×16 or ×32 Configuration Scheme—Dedicated Configuration PinsFor all pin functions in this table:
  • The I/O location is the SDM shared GPIO bank.
  • The weak pull-up or pull-down, and open drain options are not applicable.
Pin Function Direction I/O Standard Drive Strength Slew Rate
AVST_CLK Input

1.2 V LVCMOS

— —
AVST_READY Output

1.2 V LVCMOS

Series 40 Ω OCT without calibration

Medium
AVST_VALID Input

1.2 V LVCMOS

— —
AVST_DATA Input

1.2 V LVCMOS

— —
Table 40.   Intel Agilex® 7 Optional Configuration PinsThe SDM I/O for each pin function in this table is as assigned in the Intel® Quartus® Prime configuration pins option.
Pin Function Direction I/O Standard

Schmitt Trigger/

TTL Input

 Weak Pull-Up / Pull-Down Drive Strength Open Drain Slew Rate
PWRMGT_SCL Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Slow
PWRMGT_SDA Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Slow
PWRMGT_ALERT Output 1.8V LVCMOS — — 2 mA Enable Slow
CONF_DONE Output 1.8V LVCMOS — — 8 mA Disable Fast
INIT_DONE Output 1.8V LVCMOS — — 8 mA Disable Fast
CvP_CONFDONE Output 1.8V LVCMOS — — 8 mA Disable Fast
SEU_ERROR Output 1.8V LVCMOS — — 8 mA Disable Fast
HPS_COLD_nRESET Bidirectional 1.8V LVCMOS Schmitt Trigger Weak pull-up with 20 kΩ resistor 2 mA Enable Fast
Direct to factory image Input 1.8V LVCMOS Schmitt Trigger Weak pull-down with 20 kΩ resistor — — —
nCATTRIP Output 1.8V LVCMOS — — 2 mA Disable Slow
TAMPERDETECTION Output 1.8V LVCMOS — — 8 mA Disable Fast
TAMPERRESPONSESTATUS Output 1.8V LVCMOS — — 8 mA Disable Fast
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