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1. FPGA AI Suite SoC Design Example User Guide
2. About the SoC Design Example
3. FPGA AI Suite SoC Design Example Quick Start Tutorial
4. FPGA AI Suite SoC Design Example Run Process
5. FPGA AI Suite SoC Design Example Build Process
6. FPGA AI Suite SoC Design Example Quartus® Prime System Architecture
7. FPGA AI Suite Soc Design Example Software Components
8. Streaming-to-Memory (S2M) Streaming Demonstration
A. FPGA AI Suite SoC Design Example User Guide Archives
B. FPGA AI Suite SoC Design Example User Guide Document Revision History
3.1. Initial Setup
3.2. Initializing a Work Directory
3.3. (Optional) Create an SD Card Image (.wic)
3.4. Writing the SD Card Image (.wic) to an SD Card
3.5. Preparing SoC FPGA Development Kits for the FPGA AI Suite SoC Design Example
3.6. Adding Compiled Graphs (AOT files) to the SD Card
3.7. Verifying FPGA Device Drivers
3.8. Running the Demonstration Applications
7.1.1. Yocto Recipe: recipes-core/images/coredla-image.bb
7.1.2. Yocto Recipe: recipes-bsp/u-boot/u-boot-socfpga_%.bbappend
7.1.3. Yocto Recipe: recipes-drivers/msgdma-userio/msgdma-userio.bb
7.1.4. Yocto Recipe: recipes-drivers/uio-devices/uio-devices.bb
7.1.5. Yocto Recipe: recipes-kernel/linux/linux-socfpga-lts_5.15.bbappend
7.1.6. Yocto Recipe: wic
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5.1.3.1. The create_project.bash Script
The create_project.bash script has two command line options:
create_project.bash <arch> <ip_path>
The arguments must be placed in order.
- The <arch> option provides the architecture to be selected when building the SoC Example Design. Use the architecture file that was used as a command option in dla_build_example_design.py command.
The <arch> value to specify is extracted from the architecture file name:
Architecture File Name Command Line Option AGX7_Performance.arch AGX7_Performance_AGX7 AGX7_FP16_SoftMax.arch AGX_FP16_SoftMax_AGX7 A10_Performance.arch A10_Performance_A10 A10_FP16_SoftMax.arch A10_FP16_SoftMax_A10 -
The <ip_path> option provides a full path to the FPGA AI Suite IP
This script deletes the old output products, cleans the Platform Designer system, and resets the project.