FPGA AI Suite: SoC Design Example User Guide

ID 768979
Date 7/31/2024
Public
Document Table of Contents

7.4.1. MMD Layer Hardware Interaction Library Class mmd_device

This class has the following responsibilities:

  • Acquire the FPGA AI Suite IP, the stream controller (S2M only) and the mSGDMA
  • Register interrupt callback for the FPGA AI Suite IP
  • Provide read/write CSR and DDR functionality to the FPGA AI Suite runtime
  • Linux device discovery.

The class attempts discovery of the following UIO devices, each from the /sys/class/uio/ui*/ namespace.

coredla0

This represents the FPGA AI Suite IP CSR registers.

stream_controller0

If present (S2M only), this represents the Stream Controller CSR registers.

layout_transform0

If present (S2M only), this represents the Layout Transform CSR registers. Note that this device is not directly controlled from the runtime.

The class also attempts to discover the following mSGDMA-USERIO devices.

/dev/msgdma_coredla0

This represents the mSGDMA used to transfer weights, instructions, microcode, and, during M2M operation, image data.

/dev/msgdma_stream0

This represents the mSGDMA used to transfer images to the Layout Transform during the S2M mode of operation.