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Ixiasoft
2.1. FPGA AI Suite SoC Design Example Prerequisites
- Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit (4x F-Tile) (Ordering code DK-SI-AGI027FA or DK-SI-AGI027FC)
This development kit features an Agilex™ 7 I-Series SoC device with 4 F-Tiles (OPN: AGIB027R31B1E1V).
Important: The FPGA AI Suite requires DDR4 memory with an x8 or higher component data width. The RAM device provided with the Agilex™ 7 FPGA I-Series Transceiver-SoC Development Kit provides only a x4 component data width. For more details and recommended RAM modules, refer to Agilex 7 FPGA I-Series Transceiver-SoC Development Kit Hardware Requirements.For more details about this development kit, refer to the following URL: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/si-agi027.html
- Arria® 10 SX SoC FPGA Development Kit
This development kit features an Arria® 10 SX 660 device (OPN: 10AS066N3F40E2SG) with a " -2" speed grade with the included DDR4 HILO memory cards.
For more details about this development kit, refer to the following URL:
https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html
In addition, the following hardware components are required:
- SDHC flash card, class 10 speed or faster (minimum 2 GB but 4 GB or more is recommended)
- Mini-USB cable suitable for connecting the development board to a host PC
- Ethernet cable suitable for connecting the development board to a network to provide access from a host PC on the same network
The host PC must use a supported operating system (Red Hat* Enterprise Linux* 8, Ubuntu* 20.04, or Ubuntu* 22.04), and must have an internet connection to install the software dependencies.
To build bitstreams, Quartus® Prime Pro Edition Version 24.2 must be installed on the host system.
Although the development host system does not need to be the same as the system used to build packages and bitstreams, this guide does not explicitly cover the scenario where they are distinct.