Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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ID 768844
Date 10/12/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. NoC Switch and Link Detail 3.4. Fabric NoC 3.5. NoC Protocol Support 3.6. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.5. NoC Protocol Support x
3.5.1. AXI4 Protocol Support 3.5.2. AXI4 Handshaking Support 3.5.3. Quality of Service (QoS) Support 3.5.4. Transaction Ordering Support 3.5.5. AXI4-Lite Protocol Support
3.6. NoC Design Considerations x
3.6.1. Determining the Number of NoC Targets 3.6.2. Determining the Number of NoC Initiators 3.6.3. Fabric NoC Considerations 3.6.4. Latency Considerations 3.6.5. Initiator and Target Bandwidth Considerations 3.6.6. Horizontal Bandwidth Considerations 3.6.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. Making NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. NoC Design Flow Options
4.3. NoC Building Blocks x
4.3.1. NoC Initiators for Hard Processor Systems 4.3.2. NoC Targets for Hard Processor Systems 4.3.3. NoC Initiators for Fabric AXI4 Managers 4.3.4. NoC Targets for Fabric AXI4 Managers 4.3.5. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 4.4.4. Connectivity Guidelines: NoC Clock Control 4.4.5. Connectivity Guidelines: NoC Initiators for HPS 4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.4.1. General NoC IP Connectivity Guidelines x
4.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 4.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor 4.5.3. NoC Connection and Addressing Examples
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.5.3. NoC Connection and Addressing Examples x
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
4.5.3.1.1. Example 1: Platform Designer Connection Flow 4.5.3.1.2. Example 1: NoC Assignment Editor Connection Flow
4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
4.5.3.2.1. Example 2: Platform Designer Connection Flow 4.5.3.2.2. Example 2: NoC Assignment Editor Connection Flow
4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
4.5.3.3.1. Example 3: Platform Designer Connection Flow 4.5.3.3.2. Example 3: NoC Assignment Editor Connection Flow
4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
4.5.3.4.1. Example 4: Platform Designer Connection Flow 4.5.3.4.2. Example 4: NoC Assignment Editor Connection Flow
4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces x
4.5.3.5.1. Example 5: Platform Designer Connection Flow 4.5.3.5.2. Example 5: NoC Assignment Editor Connection Flow
4.6. Making NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 6.3. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor

This step describes how to create connection assignments between initiators and targets using the NoC Assignment Editor. If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, you make connections between initiators and targets in Platform Designer. The design .qip file stores those connection assignments that appear automatically in the NoC Assignment Editor as read-only assignments. You must make any changes to these assignments only in Platform Designer.

If your design uses the Platform Designer connection flow, as NoC Design Flow Options describes, and you have not made group assignments for your NoC elements, the Connection tab displays an <Ungrouped> subtab. The <Ungrouped> subtab shows connections that you defined in Platform Designer, but whose elements you have not assigned to a NoC group. Before continuing with connection assignments, click the Group tab and make group assignments for all NoC elements, as Step 1: Make Group Assignments in the NoC Assignment Editor describes.

After creating the group assignments in the Group tab of the NoC Assignment Editor, follow these steps to specify connections between NoC initiators and targets or SSM elements:

  1. In the NoC Assignment Editor, click the Connection tab. The Connection tab includes a subtab for each group that you specify on the Group tab.
    Note: You must complete the Group tab assignments before starting the Connection tab assignments.
  2. Specify connections between a NoC initiator and a target or SSM by enabling the corresponding checkbox in the connection table. The group subtab includes a connection table with all the NoC initiators for that group listed on the left-hand side, and of all the NoC targets and SSM elements for the group listed across the top.

Figure 23. NoC Assignment Editor Connection Tab shows an example Connection tab in the NoC Assignment Editor with individual initiators and targets marked for connection.

Figure 23. NoC Assignment Editor Connection Tab


Note: Use the scrollbar at the right side to view additional initiators below. Use the scrollbar along the bottom to view additional targets or SSM elements to the right.

The following shows the equivalent .qsf assignment for specifying an initiator-to-target connection: 

set_instance_assignment -name NOC_CONNECTION ON -from \
<hierarchical initiator path name> -to <hierarchical target path name>
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