Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

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Date 10/12/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Network-on-Chip (NoC) Overview 3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs 4. NoC Design Flow in Intel® Quartus® Prime Pro Edition 5. NoC Real-time Performance Monitoring 6. Simulating NoC Designs 7. NoC Power Estimation 8. Hard Memory NoC IP Reference 9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide
2. Network-on-Chip (NoC) Overview x
2.1. Introduction to Intel Agilex® 7 M-Series FPGAs 2.2. Terminology for Intel Agilex® 7 M-Series FPGAs 2.3. General NoC Architecture and Applications
2.3. General NoC Architecture and Applications x
2.3.1. General NoC Architecture 2.3.2. Example NoC Applications
2.3.2. Example NoC Applications x
2.3.2.1. Parallel Computing NoC Application 2.3.2.2. SmartNIC NoC Application
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs x
3.1. High-Level Architecture 3.2. NoC Segments 3.3. NoC Switch and Link Detail 3.4. Fabric NoC 3.5. NoC Protocol Support 3.6. NoC Design Considerations
3.2. NoC Segments x
3.2.1. UIB Segments 3.2.2. GPIO-B Segments 3.2.3. GPIO-B and HPS Segment 3.2.4. SDM Segment 3.2.5. PLL and SSM Segment
3.5. NoC Protocol Support x
3.5.1. AXI4 Protocol Support 3.5.2. AXI4 Handshaking Support 3.5.3. Quality of Service (QoS) Support 3.5.4. Transaction Ordering Support 3.5.5. AXI4-Lite Protocol Support
3.6. NoC Design Considerations x
3.6.1. Determining the Number of NoC Targets 3.6.2. Determining the Number of NoC Initiators 3.6.3. Fabric NoC Considerations 3.6.4. Latency Considerations 3.6.5. Initiator and Target Bandwidth Considerations 3.6.6. Horizontal Bandwidth Considerations 3.6.7. GPIO-B Bypass Mode and Initiators
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition x
4.1. Hard Memory NoC Design Flow Overview 4.2. Using NoC Example Designs 4.3. NoC Building Blocks 4.4. Connecting NoC IP 4.5. Making NoC Logical Assignments 4.6. Making NoC Physical Assignments Using Interface Planner 4.7. Compiling the NoC Design
4.1. Hard Memory NoC Design Flow Overview x
4.1.1. NoC Design Flow Options
4.3. NoC Building Blocks x
4.3.1. NoC Initiators for Hard Processor Systems 4.3.2. NoC Targets for Hard Processor Systems 4.3.3. NoC Initiators for Fabric AXI4 Managers 4.3.4. NoC Targets for Fabric AXI4 Managers 4.3.5. NoC Clock Control
4.4. Connecting NoC IP x
4.4.1. General NoC IP Connectivity Guidelines 4.4.2. Connectivity Guidelines: NoC Initiators for Fabric AXI4 Managers 4.4.3. Connectivity Guidelines: NoC Targets for Fabric AXI4 Managers 4.4.4. Connectivity Guidelines: NoC Clock Control 4.4.5. Connectivity Guidelines: NoC Initiators for HPS 4.4.6. Connectivity Guidelines: NoC Targets for HPS
4.4.1. General NoC IP Connectivity Guidelines x
4.4.1.1. Connecting NoC IP and Assigning Base Addresses in the Platform Designer Connection Flow 4.4.1.2. Connecting NoC IP and Assigning Base Addresses in the NoC Assignment Editor Connection Flow
4.5. Making NoC Logical Assignments x
4.5.1. Creating NoC Assignments for Compilation 4.5.2. Using the NoC Assignment Editor 4.5.3. NoC Connection and Addressing Examples
4.5.2. Using the NoC Assignment Editor x
4.5.2.1. Step 1: Make Group Assignments in the NoC Assignment Editor 4.5.2.2. Step 2: Make Connection Assignments in the NoC Assignment Editor 4.5.2.3. Step 3: Make Attribute Assignments in the NoC Assignment Editor 4.5.2.4. Step 4: Validate Logical NoC Assignments and Generate Simulation File
4.5.3. NoC Connection and Addressing Examples x
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator 4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator 4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator 4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator 4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces
4.5.3.1. Example 1: External Memory Interface with 1 AXI4 Initiator and 1 AXI4-Lite Initiator x
4.5.3.1.1. Example 1: Platform Designer Connection Flow 4.5.3.1.2. Example 1: NoC Assignment Editor Connection Flow
4.5.3.2. Example 2: Two External Memory Interfaces with One AXI4 Initiator and One AXI4-Lite Initiator x
4.5.3.2.1. Example 2: Platform Designer Connection Flow 4.5.3.2.2. Example 2: NoC Assignment Editor Connection Flow
4.5.3.3. Example 3: One External Memory Interfaces with Two AXI4 Initiators and One AXI4-Lite Initiator x
4.5.3.3.1. Example 3: Platform Designer Connection Flow 4.5.3.3.2. Example 3: NoC Assignment Editor Connection Flow
4.5.3.4. Example 4: Two High-Bandwidth Memory Pseudo-Channels with Two AXI4 Initiators (Crossbar) and Shared AXI4-Lite Initiator x
4.5.3.4.1. Example 4: Platform Designer Connection Flow 4.5.3.4.2. Example 4: NoC Assignment Editor Connection Flow
4.5.3.5. Example 5: Hard Processor System with Two External Memory Interfaces x
4.5.3.5.1. Example 5: Platform Designer Connection Flow 4.5.3.5.2. Example 5: NoC Assignment Editor Connection Flow
4.6. Making NoC Physical Assignments Using Interface Planner x
4.6.1. Using Interface Planner 4.6.2. Recommended Placement Order for NoC Elements in Interface Planner 4.6.3. Hard Memory NoC Locations in Interface Planner 4.6.4. NoC Performance Reports in Interface Planner
4.7. Compiling the NoC Design x
4.7.1. Fitter NoC Reports 4.7.2. Viewing NoC Elements in Chip Planner
6. Simulating NoC Designs x
6.1. Generating a Simulation Registration Include File (Platform Designer Connection Flow) 6.2. Generating a Simulation Registration Include File (NoC Assignment Editor Connection Flow) 6.3. Contents of Simulation Registration Include File
7. NoC Power Estimation x
7.1. Using the Intel FPGA PTC to Estimate NoC Power
8. Hard Memory NoC IP Reference x
8.1. NoC Initiator Intel FPGA IP 8.2. NoC Clock Control Intel FPGA IP
8.1. NoC Initiator Intel FPGA IP x
8.1.1. NoC Initiator Intel FPGA IP Parameters 8.1.2. NoC Initiator Intel FPGA IP Interfaces
8.1.2. NoC Initiator Intel FPGA IP Interfaces x
8.1.2.1. NoC Initiator Intel FPGA IP AXI4/AXI4-Lite Interfaces 8.1.2.2. NoC Initiator AXI4 User Interface Signals 8.1.2.3. NoC Initiator Intel FPGA IP AXI4-Lite User Interface Signals 8.1.2.4. NoC Initiator Intel FPGA IP Clock and Reset Signals 8.1.2.5. NoC Initiator Intel FPGA IP Platform Designer-Only Signals
8.2. NoC Clock Control Intel FPGA IP x
8.2.1. NoC Clock Control Intel FPGA IP Parameters 8.2.2. NoC Clock Control Intel FPGA IP Interfaces 8.2.3. NoC Clock Control Intel FPGA IP Platform Designer-only Signals
1. Answers to Top FAQs
2. Network-on-Chip (NoC) Overview
3. Hard Memory NoC in Intel Agilex® 7 M-Series FPGAs
4. NoC Design Flow in Intel® Quartus® Prime Pro Edition
5. NoC Real-time Performance Monitoring
6. Simulating NoC Designs
7. NoC Power Estimation
8. Hard Memory NoC IP Reference
9. Document Revision History of Intel Agilex® 7 M-Series FPGA Network-on-Chip (NoC) User Guide

8.1.2.2. NoC Initiator AXI4 User Interface Signals

This section describes the signals for the AXI4 interfaces. The AXI4 read-only and write-only interfaces are subsets of the standard AXI4 interface. Depending on the IP configuration, the signal prefix can be s<x>_axi4_, s<x>_ro_axi4_, or s<x>_wo_axi4_, for example s0_axi4_awid.

AXI ID signals exposed by the NoC Initiator Intel FPGA IP are seven bits wide, unless the NoC Initiator Intel FPGA IP is also exposing AXI4 Lite interfaces. When you configure the NoC Initiator Intel FPGA IP to expose AXI4 Lite interfaces, AXI ID signals on its AXI4 interfaces are six bits wide.

Table 14.  AXI4 Write Address (AW) Command Channel
Port Name Width Direction Description
<prefix>_awid 7 or 6 Input Write transaction identification tag for the write command.
<prefix>_awaddr 44 Input Write Address. The write address gives the address of the first transfer in a write burst transaction.
<prefix>_awlen 8 Input

Burst Length. The burst length gives the exact number of transfers in the AXI4 write transaction. This information determines the number of data transfers associated with the address. awlen is encoded as (<number of transfers> - 1).

<prefix>_awsize 3 Input

Size. This signal indicates number of bytes written by each transfer in the burst. For write data widths of 256 bits or less, awsize must indicate a width less than or equal to the width of wdata.

awsize is encoded as follows:

3'b000 = 1 byte

3'b001 = 2 bytes

3'b010 = 4 bytes

3'b011 = 8 bytes

3'b100 = 16 bytes

3'b101 = 32 bytes

3'b110 = 64 bytes (512-bit initiators must drive awsize to 3'b110).

Note: If the write data width is 512 bits, this signal must have the value 3'b110.
<prefix>_awburst 2 Input

Burst Type. The burst type and the size information determine how to calculate the address for each transfer within the burst .

  • 2’b01 = INCR burst type

Only INCR is supported. 2'b00 = FIXED and 2'b10 = WRAP are not supported. 2'b11 is reserved and does not decode to anything

<prefix>_awlock 1 Input

Lock Type [reserved for future use].

  • 1’b0 = Normal access (no lock)
<prefix>_awprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

  • 3’b010 = Unprivileged, non-secure data access
<prefix>_awqos 4 Input Quality of Service. The quality of service identifier sent for each write transaction. For the upper two bits, 3=highest, 0= lowest. The lower two bits are ignored. Refer to Quality of Service (QoS) Support.
<prefix>_awuser 11 Input User signal. Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 M-Series FPGA IP User Guide or the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide for how to optionally map this signal for transactions with each IP. Tie unused bits low. The width of this signal may change in future releases of the IP.
<prefix>_awvalid 1 Input Write Address Valid. This signal indicates that the host or manager is signaling valid write address and control information. The write address valid signal must not be dependent on the write address ready signal.
<prefix>_awready 1 Output Write Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 15.  AXI4 Write Data (W) Channel
Port Name Width Direction Description
<prefix>_wdata 32, 64, 128, 256, or 512 Input Write Data. Width is determined by your selected AXI4 Data Mode.
<prefix>_wstrb 4, 8, 16, 32, or 64 Input Write Strobes (Byte Enables). These signals indicate which bytes of the AXI4 wdata hold valid data. There is one byte strobe for every eight bits of write data. Write strobes are ignored when you choose an AXI4 Data Mode that has a 288 or 576 bit wide write data path.
<prefix>_wuser_data 32 or 64 Input Extra Write Data (AXI4 WUSER port). When you select an AXI4 Data Mode that has a 288 or 576 bit wide write data path, then this signal carries an additional 32 or 64 bits over the hard memory NoC. You must configure the targeted memory controller IP to store the additional bits. This signal is ignored when the AXI4 Data Mode specifies a write data width other than 288 or 576 bits.
<prefix>_wlast 1 Input Write Last. This signal indicates the last transfer in a write burst.
<prefix>_wvalid 1 Input Write Valid. This signal indicates that valid write data and accompanying strobes or user data are available. The write address valid signal must not be dependent on the write address ready signal.
<prefix>_wready 1 Output Write Ready. This signal indicates that the subordinate can accept write data.
Table 16.  AXI4 Write Response (B) Channel
Port Name Width Direction Description
<prefix>_bid 7 or 6 Output Write Response ID tag. This matches the transaction ID tag of the original write command.
<prefix>_bresp 2 Output

Write Response. This signal indicates the status of the write transaction.

  • 2’b00 = OKAY; indicates that normal access is successful.
  • 2’b10 = SLVERR; indicates an unsuccessful transaction.
  • 2'b11 = DECERR; indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original write command. Note that 2'b01 = EXOKAY is not returned as implementation does not support exclusive access.
<prefix>_bvalid 1 Output Write Response Valid. This signal indicates that the host or manager is signaling a valid write response.
<prefix>_bready 1 Input Response Ready. This signal indicates that the manager can accept a write response.
Table 17.  AXI4 Read Address (AR) command Channel
Port Name Width Direction Description
<prefix>_arid 7 or 6 Input Read transaction identification tag for the read command.
<prefix>_araddr 44 Input Read Address. The address of the first transfer in a read burst transaction.
<prefix>_arlen 8 Input

Burst Length. The burst length gives the exact number of transfers in the AXI4 transaction. This information determines the number of data transfers associated with the address.

arlen is encoded as (<number of transfers> - 1).
<prefix>_arsize 3 Input

Size. This signal indicates the number of bytes written by each transfer in the burst. If the read data width is 512 bits, this signal must have the value 3'b110. For read data widths of 256 bits or less, arsize must indicate a width less than or equal to the width of rdata. arsize is encoded as follows:

3'b000 = 1 byte

3'b001 = 2 bytes

3'b010 = 4 bytes

3'b011 = 8 bytes

3'b100 = 16 bytes

3'b101 = 32 bytes

3'b110 = 64 bytes
<prefix>_arburst 2 Input

Burst Type. The burst type and the size information determines how the address for each transfer within the burst is calculated.

  • 2’b01 = INCR burst type

Only INCR is supported.

<prefix>_arlock 1 Input

Lock Type [reserved for future use].

1’b0 = Normal access (no lock)

<prefix>_arprot 3 Input

Protection Type [reserved for future use]. This signal indicates the privilege and security level of the transaction, and whether the transaction is a data access or an instruction access.

3’b010 = Unprivileged, non-secure data access

<prefix>_arqos 4 Input Quality of Service. The quality of service identifier sent for each read transaction.
<prefix>_aruser 11 Input User signal. Refer to the High Bandwidth Memory (HBM2E) Interface Intel Agilex 7 M-Series FPGA IP User Guide or the External Memory Interfaces Intel Agilex 7 M-Series FPGA IP User Guide for how to optionally map this signal for transactions with each IP. Tie unused bits low. The width of this signal may change in future releases of the IP.
<prefix>_arvalid 1 Input Read Address Valid. This signal indicates that the channel is signaling valid read address and control information.
<prefix>_arready 1 Output Read Address Ready. This signal indicates that the subordinate is ready to accept an address and associated control signals.
Table 18.  AXI4 Read Data (R) Channel
Port Name Width Direction Description
<prefix>_rid 7 or 6 Output Read Response ID tag. This matches the transaction ID tag of the original read command.
<prefix>_rdata 32, 64, 128, 256, or 512 Output Read Data. Width is determined by the selected AXI4 Data Mode.
<prefix>_rresp 2 Output

Read Response. This signal indicates the status of the read transfer:

  • 2’b00 = OKAY
  • 2’b10 = SLVERR: indicates an unsuccessful transaction.
  • 2'b11 = DECERR: indicates that the hard memory NoC could not extract a valid destination address from the address supplied in the original read command. Note that 2'b01 = EXOKAY is not returned as implementation does not support exclusive access.
<prefix>_ruser 32 0r 64 Output When you select an AXI4 Data Mode that has a 288 or 576 bit wide read data path, then this signal carries an additional 32 or 64 bits that are returned across the hard memory NoC. You must configure the targeted memory controller IP to read and return the additional bits. This signal does not contain valid data when the AXI4 Data Mode specifies a read data width other than 288 or 576 bits.
<prefix>_rlast 1 Output Read Last. This signal indicates the last transfer in a read burst.
<prefix>_rvalid 1 Output Read Valid. The read address valid signal must not be dependent on the read address ready signal.
<prefix>_rready 1 Input Read Ready. This signal indicates that the manager can accept the read data and response information.
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