MACsec Intel FPGA System Design User Guide

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ID 767516
Date 3/03/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Architecture 3. Interface Overview 4. Parameters 5. Configuration Registers 6. Software Architecture 7. Generating the System Design 8. Document Revision History for MACsec System Design User Guide
1. Introduction x
1.1. Terminology 1.2. Release Information 1.3. System Requirements
2. Architecture x
2.1. System Architecture 2.2. Data Path Between Ethernet MAC and MACsec 2.3. Data Path Between MACsec and MCDMA 2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client) 2.5. Data Path Illustrations 2.6. Interrupts 2.7. Packet FIFO 2.8. AXI-ST Rate Controller 2.9. Error Handling 2.10. Top Level Signals
2.2. Data Path Between Ethernet MAC and MACsec x
2.2.1. Ethernet Subsystem
2.2.1. Ethernet Subsystem x
2.2.1.1. Data Receiving from MACsec to E/F-Tile Hard IP 2.2.1.2. Data Transmitting from E/F-tile Hard IP to MACsec 2.2.1.3. Order of Ethernet Transmission 2.2.1.4. E/F-Tile Hard IP Reset Sequence
2.3. Data Path Between MACsec and MCDMA x
2.3.1. AXI-ST Multi-Segment to Single-Segment Conversion 2.3.2. MCDMA
2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client) x
2.4.1. Packet Client 2.4.2. Packet Generation and Check
2.5. Data Path Illustrations x
2.5.1. MACsec Interface Signal Names
2.6. Interrupts x
2.6.1. MCDMA MSI-X Table Configuration
3. Interface Overview x
3.1. Clocking 3.2. Resets
5. Configuration Registers x
5.1. System Register Map
5.1. System Register Map x
5.1.1. Packet Client Register Map 5.1.2. Interrupt Controller Register Map
6. Software Architecture x
6.1. MACsec Key Agreement Protocol 6.2. Driver Functional Requirements 6.3. Software Requirements 6.4. Software Overview 6.5. MACsec IP APIs Sequence 6.6. Functions 6.7. Software Tools
6.4. Software Overview x
6.4.1. McDMA Driver Kernel Module 6.4.2. MACsec IP APIs 6.4.3. Linux MACsec Driver Kernel Module 6.4.4. IP Tool 6.4.5. WPA Supplicant
6.4.2. MACsec IP APIs x
6.4.2.1. SDK
6.5. MACsec IP APIs Sequence x
6.5.1. MACsec Initialization Sequence
6.5.1. MACsec Initialization Sequence x
6.5.1.1. MACsec Reset Sequence 6.5.1.2. TX Configuration Sequence 6.5.1.3. RX Configuration Sequence 6.5.1.4. TX Rekeying Sequence 6.5.1.5. RX Rekeying Sequence 6.5.1.6. Cut Through/Store Forward Mode 6.5.1.7. User Single/Multi Port Settings 6.5.1.8. Encrypt/Decrypt Port 6.5.1.9. Port Priority 6.5.1.10. Interrupt Generation and Register
6.5.1.1. MACsec Reset Sequence x
6.5.1.1.1. GLOBAL Reset 6.5.1.1.2. PORT Reset 6.5.1.1.3. Secure Association (SA) Reset
6.6. Functions x
6.6.1. macsec_initilize 6.6.2. macsec_get_attributes 6.6.3. macsec_get_sa_attributes 6.6.4. macsec_set_attributes 6.6.5. macsec_set_sa_attributes 6.6.6. macsec_read_register 6.6.7. macsec_write_register 6.6.8. macsec_set_port_configuration 6.6.9. macsec_rate_configuration 6.6.10. macsec_single_or_multi_port 6.6.11. macsec_crypto_mode 6.6.12. macsec_port_priority 6.6.13. macsec_register_isr
6.7. Software Tools x
6.7.1. IP Tool 6.7.2. WPA_Supplicant 6.7.3. CLI Debug Tool
6.7.3. CLI Debug Tool x
6.7.3.1. Functional Requirements 6.7.3.2. Features Overview 6.7.3.3. Design with HOST 6.7.3.4. Netlink Interface 6.7.3.5. SDK 6.7.3.6. Design Overview
7. Generating the System Design x
7.1. Software Requirements 7.2. Obtaining the Reference Design 7.3. Reference Design Directory Structure 7.4. Simulation Command Arguments 7.5. Simulation Test Cases 7.6. Complete Simulation Command 7.7. Simulation Requirements 7.8. Running the Simulation 7.9. Building, Installing, and Running the Software
7.4. Simulation Command Arguments x
7.4.1. Simulation -d Options
1. Introduction
2. Architecture
3. Interface Overview
4. Parameters
5. Configuration Registers
6. Software Architecture
7. Generating the System Design
8. Document Revision History for MACsec System Design User Guide

7.8. Running the Simulation

The design simulation for checking the Reference Design’s functionality is done in the sim/ directory, which contains the necessary files for the simulation.

The <Project_Directory>/release)1p0/MACSEC_Release_1.0/MACSEC_SysED_Instruction_Readme_1.0.txt file contains the steps to run the simulation.

The steps for running the simulation are provided below.
  1. Navigate to the env/ directory.
  2. Source the environment settings. This is to be done only once in a shell.

    -- source setup.sh

  3. For E-tile there is no need for support logic generation, but for F-tile designs follow the steps below for supporting logic generation.
    • Go to $SRD_ROOTDIR/sim/common and source the script below for the appropriate support logic generation for F-tile based design.
      1. Support logic generation 25G full design:

        sh support_logic_gen.sh agx_nr_mudv 25G

      2. Support logic generation 25G Lightweight MCDMA BFM design:

        sh support_logic_gen.sh agx_nr_mudv 25G 1

      3. Support logic generation 100G full design:

        sh support_logic_gen.sh agx_nr_mudv 100G

      4. Support logic generation 100G Lightweight MCDMA BFM design:

        sh support_logic_gen.sh agx_nr_mudv 100G 1

  4. For E-tile based design simulation: Go to $SRD_ROOTDIR/sim/common_ptile.

    For F-tile based design simulation: Go to $SRD_ROOTDIR/sim/common.

    Source the script generate_ip.sh, for IP simulation files generation.

    The ip_list.f contains the list of all IPs used in the design.

    sh generate_ip.sh ip_list.f

  5. Navigate to the sim/runDir directory.
  6. Run the simulation using the ./run_sim.sh command with arguments. The supported arguments are shown in Simulation Command Arguments. The test cases are provided in the sim/testcase folder. Each test case has the test description mentioned in the first few lines of the file.

The following figure represents a typical run of the “combinedTrafficTest.sv” test:


TBINFO: address = 0a000034, readdata = 00000000
TBINFO: address = 0a000038, readdata = 00000000
TBINFO: address = 0a000058, readdata = 00000000
TBINFO: address = 0a000060, readdata = 00010000
TBINFO: address = 0a000064, readdata = 00000000
TBINFO: address = 0a000068, readdata = 00022df8
TBINFO: address = 0a00006c, readdata = 00000000
TBINFO: address = 0a000070, readdata = 000045bf
TBINFO: address = 0a000074, readdata = 00000000
TBINFO: address = 0a000078, readdata = 00004b72
TBINFO: address = 0a00007c, readdata = 00000000
TBINFO: address = 0a000000, readdata = 00000651
TBINFO: address = 0a000000, writedata32 = 00000611
TBINFO: Function 1 Clearing Packet Client Stats
TBINFO: address = 0a000000, readdata = 00000611
TBINFO: address = 0a000000, writedata32 = 00000699
TBINFO: address = 0a000000, readdata = 00000699
TBINFO: address = 0a000000, writedata32 = 00000611
TBINFO: Function 1 TX/RX packet check OK
*** TX PERFORMANCE MEASUREMENT *** no. of bytes = 0x22df8 num_ticks = 0x45bf perf_data = 25.6000 Gb/s
*** RX PERFORMANCE MEASUREMENT *** no. of bytes = 0x10000 num_ticks = 0x4b72 perf_data = 10.8582 Gb/s
TBINFO: Function 1 Stop pkt gen TX
TBINFO: address = 0a000000, writedata32 = 00000100

TBINFO: *****************************************
TBINFO: Simulation Passed.
TBINFO: Testbench complete
TBINFO: *****************************************

$finish called from file "../../tbTop/tb_macsec_srd.sv", line 125.
$finish at simulation time 522309564000

Following a successful simulation, a subdirectory is created in the /runDir directory which corresponds to the test just run.

For example, the following directory is created for the “combinedTrafficTest.sv” test:

<project directory>/sim/runDir/combinedTrafficTest

Within this test-specific directory, you can find all log files for the test as well as a .vpd file (if you used the -m 1 simulation argument) which allows you to bring up waves for the test run using the Synopsys DVE tool.

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