Visible to Intel only — GUID: bgr1672948494462
Ixiasoft
Visible to Intel only — GUID: bgr1672948494462
Ixiasoft
5.1.1. Packet Client Register Map
Offset | Name | Bit | Type | HW Reset Value | Description |
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0x000 | CFG_PKT_CL_CTRL | [31:20] | RO | 23’b0 | Reserved. |
[19:12] | RW | 8’b0 | Number of Idle cycles to be inserted between packets. Applicable in dynamic mode when CFG_PKT_CL_CTRL[9] is set to 1. |
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[11:10] | RW | 2’b00 | 00: Reserved (Random). 01: Fixed length mode. 10: Incremental length mode. 11: Reserved. Only applicable in dynamic packet gen mode. |
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[9] | RW | 1’b0 | 0: For transmission with random gap in between packets. Only applicable in Dynamic packet gen mode. 1: For transmission with fixed gap in between packets. |
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[8] | RW | 1’b0 | When set to ‘1’, it clears Internal Tx & Rx Status counters. Once set to ‘1’, CPU must clear this bit afterwards. | ||
[7] | RW | 1’b0 | When set to ‘1’, it clears Tx & Rx Status counter CSRs. Once set to ‘1’, CPU must clear this bit afterwards. | ||
[6] | RW | 1’b0 | When set to ‘1’, it takes snapshot of Internal Tx & Rx Status counters to CSRs. Once set to ‘1’, CPU must clear this bit. | ||
[5] | RW | 1’b0 | 0: Disable Packet checker .1: Enable Packet checker. Checker block generates reference data based on its own packet generator setting. |
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[4] | RW | 1’b0 | 0: Reserved. 1: Select dynamic mode packet generation. |
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[3] | RW | 1’b0 | 0: Deassert checker/packetgen soft reset. 1: Assert checker/packetgen soft reset CSR block is not reset by this soft reset. Use this to soft reset blocks after a sequence execution. |
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[2] | RW | 1’b0 | 0: Generates traffic in one shot mode. 1: Reserved. |
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[1] | RO | 1’b0 | Reserved. |
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[0] | RW | 1’b0 | 1: Tx Traffic is enabled from packet client. 0: Tx traffic is disabled from packet client. |
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0x004 | RESERVED |
[31:16] | |||
[15:0] | |||||
0x008 | RESERVED |
[31:16] | |||
[15:0] | |||||
0x00C | DYN_DMAC_ADDR_U | [31:16] | RO | 0x0 | Reserved. |
[15:0] | RW | 0x1234 | Destination MAC address (upper 16 bits). Only applicable in dynamic packet mode. |
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0x010 | DYN_DMAC_ADDDR_L | [31:0] | RW | 0x56780A DD |
Destination MAC address (lower 32 bits). Only applicable in dynamic packet gen mode. |
0x014 | DYN_SMAC_ADDR_U | [31:16] | RO | 0x0 | Reserved. |
[15:0] | RW | 0x8765 | Source MAC address (upper 16 bits). Only applicable in dynamic packet gen mode. |
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0x018 | DYN_SMAC_ADDR_L | [31:0] | RW | 0x0x4321 0ADD |
Source MAC address (lower 32 bits). Only applicable in dynamic packet mode. |
0x01C | DYN_PKT_NUM | [31:0] | RW | 0xA | Specifies the number of packets to transmit from the packet generator. Only applicable in dynamic packet gen mode. |
0x020 | DYN_PKT_SIZE_CFG | [31:30] | RO | 0x0 | |
[29:16] | RW | 0x2580 | Specifies the transmit packet size in bytes. Specifies the upper limit of the packet size in bytes. This is only applicable to incremental mode within dynamic gen packet mode. |
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[15:14] | RO | 0x0 | Reserved. | ||
[13:0] | RW | 0x0040 | Specifies the transmit packet size in bytes. For fixed mode, these bits specify the transmit packet size in bytes. For incremental mode, these bits specify the incremental bytes for a packet. Only applicable in dynamic packet gen mode. |
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0x024 | STAT_TX_SOP_CNT_L | [31:0] | RO | 32’b0 | TX Start of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x028 | STAT_TX_SOP_CNT_U | [31:0] | RO | 32’b0 | TX Start of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x02C | STAT_TX_SOP_CNT_L | [31:0] | RO | 32’b0 | TX End of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x030 | STAT_TX_SOP_CNT_U | [31:0] | RO | 32’b0 | TX End of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x034 | STAT_TX_ERR_CNT_L | [31:0] | RO | 32’b0 | TX Error counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x038 | STAT_TX_ERR_CNT_U | [31:0] | RO | 32’b0 | TX Error counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x03C | STAT_RX_SOP_CNT_L | [31:0] | RO | 32’b0 | RX Start of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x040 | STAT_RX_SOP_CNT_U | [31:0] | RO | 32’b0 | RX Start of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x044 | STAT_RX_EOP_CNT_L | [31:0] | RO | 32’b0 | RX End of packet counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x048 | STAT_RX_EOP_CNT_U | [31:0] | RO | 32’b0 | RX End of packet counter upper 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x04C | STAT_RX_ERR_CNT_L | [31:0] | RO | 32’b0 | RX Error counter lower 32bits. CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x050 | STAT_RX_ERR_CNT_U | [31:0] | RO | 32’b0 | RX Error counter upper 32bits CPU may clear this CSR by setting CFG_PKT_CL_CTRL[7] to ‘1’. |
0x054 | STAT_SYSTEM_MISC | [31:5] | RO | 31’b0 | Reserved. |
[4] | RO | 1’b0 | 0: HSSI SS rx_pcs_ready is not asserted. 1: HSSI SS rx_pcs_ready is asserted. |
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[3] | RO | 1’b0 | 0: HSSI SS tx_pll_locked is not asserted. 1: HSSI SS tx_pll_locked is asserted. |
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[2] | RO | 1’b0 | 0: HSSI SS tx_lanes_stable is not asserted. 1: HSSI SS tx_lanes_stable is asserted. |
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[1] | RO | 1’b0 | 0: System Reset Sequence is not complete. 1: System Reset Sequence is complete. |
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[0] | RO | 1’b0 | 0: SADB Configuration is not complete. 1: SADB Configuration is complete. |
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0x058 | STAT_CHECKER_MISC | [31:1] | RO | 28’b0 | Reserved. |
[1] | RO | 1’b0 | Reserved. | ||
[0] | RO | 1’b0 | 1: Data mismatches at data checker. 0: Data does not mismatch. |
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0x05C | STAT_CHECKER_CNT | [31:1] | RO | 32’b0 | Live Packet count received at the checker. |
0x060 | PKTCLI_RX_BYTE_CNT_L | [31:0] | RO | 32’h0 | Lower bits for counter to count number of bytes received. |
0x064 | PKTCLI_RX_BYTE_CNT_U | [31:0] | RO | 32’h0 | Upper bits for counter to count number of bytes received. |
0x068 | PKTCLI_TX_BYTE_CNT_L | [31:0] | RO | 32’h0 | Lower bits for counter to count number of bytes sent. |
0x06C | PKTCLI_TX_BYTE_CNT_U | [31:0] | RO | 32’h0 | Upper bits for counter to count number of bytes sent. |
0x070 | PKTCLI_TX_NUM_TICKS_L | [31:0] | RO | 32’h0 | Number of clock cycles for all the packets to be sent. (lower bits). |
0x074 | PKTCLI_TX_NUM_TICKS_U | [31:0] | RO | 32’h0 | Number of clock cycles for all the packets to be sent. (upper bits). |
0x078 | PKTCLI_RX_NUM_TICKS_L | [31:0] | RO | 32’h0 | Number of clock cycles for all the packets to be received. (lower bits). |
0x07C | PKTCLI_RX_NUM_TICKS_U | [31:0] | RO | 32’h0 | Number of clock cycles for all the packets to be received. (upper bits). |