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Ixiasoft
2.1. System Architecture
2.2. Data Path Between Ethernet MAC and MACsec
2.3. Data Path Between MACsec and MCDMA
2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client)
2.5. Data Path Illustrations
2.6. Interrupts
2.7. Packet FIFO
2.8. AXI-ST Rate Controller
2.9. Error Handling
2.10. Top Level Signals
6.5.1.1. MACsec Reset Sequence
6.5.1.2. TX Configuration Sequence
6.5.1.3. RX Configuration Sequence
6.5.1.4. TX Rekeying Sequence
6.5.1.5. RX Rekeying Sequence
6.5.1.6. Cut Through/Store Forward Mode
6.5.1.7. User Single/Multi Port Settings
6.5.1.8. Encrypt/Decrypt Port
6.5.1.9. Port Priority
6.5.1.10. Interrupt Generation and Register
6.6.1. macsec_initilize
6.6.2. macsec_get_attributes
6.6.3. macsec_get_sa_attributes
6.6.4. macsec_set_attributes
6.6.5. macsec_set_sa_attributes
6.6.6. macsec_read_register
6.6.7. macsec_write_register
6.6.8. macsec_set_port_configuration
6.6.9. macsec_rate_configuration
6.6.10. macsec_single_or_multi_port
6.6.11. macsec_crypto_mode
6.6.12. macsec_port_priority
6.6.13. macsec_register_isr
7.1. Software Requirements
7.2. Obtaining the Reference Design
7.3. Reference Design Directory Structure
7.4. Simulation Command Arguments
7.5. Simulation Test Cases
7.6. Complete Simulation Command
7.7. Simulation Requirements
7.8. Running the Simulation
7.9. Building, Installing, and Running the Software
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Ixiasoft
7. Generating the System Design
This chapter discusses how to obtain, simulate, build, and run the System Design on hardware. The design supports different flavors of Tile combinations with different data rate support. The design is flexible enough to be configured for an E-Tile or an F-Tile based MAC with 25G or 100G data rate support using compile time directives as shown in the sections below.