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2.1. System Architecture
2.2. Data Path Between Ethernet MAC and MACsec
2.3. Data Path Between MACsec and MCDMA
2.4. Data Path Between MACsec and Packet Generator/Checker (Packet Client)
2.5. Data Path Illustrations
2.6. Interrupts
2.7. Packet FIFO
2.8. AXI-ST Rate Controller
2.9. Error Handling
2.10. Top Level Signals
6.5.1.1. MACsec Reset Sequence
6.5.1.2. TX Configuration Sequence
6.5.1.3. RX Configuration Sequence
6.5.1.4. TX Rekeying Sequence
6.5.1.5. RX Rekeying Sequence
6.5.1.6. Cut Through/Store Forward Mode
6.5.1.7. User Single/Multi Port Settings
6.5.1.8. Encrypt/Decrypt Port
6.5.1.9. Port Priority
6.5.1.10. Interrupt Generation and Register
6.6.1. macsec_initilize
6.6.2. macsec_get_attributes
6.6.3. macsec_get_sa_attributes
6.6.4. macsec_set_attributes
6.6.5. macsec_set_sa_attributes
6.6.6. macsec_read_register
6.6.7. macsec_write_register
6.6.8. macsec_set_port_configuration
6.6.9. macsec_rate_configuration
6.6.10. macsec_single_or_multi_port
6.6.11. macsec_crypto_mode
6.6.12. macsec_port_priority
6.6.13. macsec_register_isr
7.1. Software Requirements
7.2. Obtaining the Reference Design
7.3. Reference Design Directory Structure
7.4. Simulation Command Arguments
7.5. Simulation Test Cases
7.6. Complete Simulation Command
7.7. Simulation Requirements
7.8. Running the Simulation
7.9. Building, Installing, and Running the Software
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2.3. Data Path Between MACsec and MCDMA
The datapath at MCDMA interface is AVST with an additional channel ID signal which differentiates between the PF/VF groups. Your logic should have a mapping table and routing logic to MUX and DeMUX the packets. This can be done in either AVST or AXI-ST (post bridge logic) interfaces. The solution’s ecosystem supports an AXI-St MUX/DeMUX block which you can leverage. Map the AVST Channel ID as AXI-St TID if ID is supported.
Figure 13. MACSec(s) to MCDMA Path
Figure 14. Timing Diagram for Packet Boundary Alignment (Pkt FIFO in AVST)
The bridge logic shown in Figure 13 above between the MACsec and the MCDMA supports a few functions as mentioned below:
- The MACsec AXI-St interface supports multi-packet mode where a packet can start at a next segment when the current packet ends. But the MCDMA’s AVST interface treats the entire bus as single segment.Therefore, there is conversion logic which converts multi-packet to single packet in AXI-St first. This conversion also eases the packet filtering logic at a fixed bit fields during the start of a packet.
- This path includes CDC FIFOs (DC FIFO) in both the directions to accommodate the clock domain crossing between MACsec 400MHz and MCDMA 250/500 MHz. This interface is 512-bits wide.
- The MACsec expects AXI-St valid not be de-asserted in between a packet’s SOP and EOP unless Ready is deasserted. Therefore, a complete packet must be available in the FIFO before asserting Valid on the MACsec AXI-St RX interface of an uncontrolled port using a packet FIFO.
- Handling the packets from the MACsec TX uncontrolled port to MCDMA path as handshake is not supported. Therefore, you need to either drop the packet or maintain a bigger buffer. Consider a scenario where the packet is in flight and the buffer gets filled. To avoid such issues, write a packet into a buffer only when the empty space in buffer is higher than the MTU (Ethernet packet size). Assume MCDMA is already prepopulated with a descriptor for D2H Transfer.
- It is understood that MACsec forwards all its received packets on decryption line to uncontrolled RX interface, without any type of filtering. The encrypted packets are also routed in this manner. Your logic should implement packet filtering based on the required Ether type. An example would be dropping every packet when Ether type is not 0x888E(EAPOL).
Certain applications might require Gen4x8 instead of the Gen4x16 PCIe configuration. For these cases there can be an adaptor block that converts 256-bit user interface to 512-bit user interface to retain the logic which targets the Gen4x16 PCIe MCDMA.