F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

ID 758946
Date 1/09/2024
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3. Transceivers

The transceiver provides physical lane with the line rate of 25.78125 Gbps.
Table 12.  Transceiver Signals

Signal

Direction

Description

O_tx_serial Output TX transceiver signal. Each tx_serial bit becomes two physical pins that form a differential pair.
i_rx_serial Input RX transceiver signals. Each rx_serial bit becomes two physical pins that form a differential pair.