F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

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ID 758946
Date 1/09/2024
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Document Table of Contents
Document Table of Contents x
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide 2. About this IP 3. Getting Started 4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters 5. Functional Description 6. Reset 7. Interfaces and Signal Descriptions 8. Control, Status, and Statistics Register Descriptions 9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP x
2.1. Release Information 2.2. Features 2.3. Device Family Support 2.4. Performance and Resource Utilization
3. Getting Started x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. Specifying the IP Core Parameters and Options 3.3. Simulating the IP Core 3.4. Generated File Structure 3.5. Integrating Your IP Core in Your Design 3.6. Compiling the Full Design and Programming the FPGA
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode
3.5. Integrating Your IP Core in Your Design x
3.5.1. Pin Assignments 3.5.2. Adding the F-Tile Reference and System PLL Clocks Intel® FPGA IP 3.5.3. Placement Settings for the 50G Ethernet Intel FPGA IP Core
5. Functional Description x
5.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Functional Description 5.2. User Interface to Ethernet Transmission
5.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Functional Description x
5.1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX MAC Datapath 5.1.2. 50 GbE TX PCS 5.1.3. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Core RX MAC Datapath 5.1.4. Link Fault Signaling Interface 5.1.5. 50 GbE RX PCS 5.1.6. Flow Control
5.1.1. F-Tile Low Latency 50G Ethernet Intel® FPGA IP TX MAC Datapath x
5.1.1.1. Frame Padding 5.1.1.2. Preamble Insertion 5.1.1.3. Inter-Packet Gap Generation and Insertion 5.1.1.4. Frame Check Sequence (CRC32) Insertion
5.1.3. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Core RX MAC Datapath x
5.1.3.1. IP Core Preamble Processing 5.1.3.2. IP Core Malformed Packet Handling 5.1.3.3. Length/Type Field Processing
5.1.3.3. Length/Type Field Processing x
5.1.3.3.1. Length Checking 5.1.3.3.2. RX CRC Checking and Dynamic Forwarding
5.1.6. Flow Control x
5.1.6.1. TX Pause/PFC Flow Control Frame Transmission Request 5.1.6.2. XON/XOFF Pause Frames
5.2. User Interface to Ethernet Transmission x
5.2.1. Order of Transmission 5.2.2. Bit Order For TX and RX Datapaths
7. Interfaces and Signal Descriptions x
7.1. TX MAC Interface to User Logic 7.2. RX MAC Interface to User Logic 7.3. Transceivers 7.4. Transceiver Reconfiguration Signals 7.5. Avalon® Memory-Mapped Management Interface 7.6. Miscellaneous Status and Debug Signals 7.7. Flow Control Signals 7.8. Clock Signals 7.9. Reset Signals
8. Control, Status, and Statistics Register Descriptions x
8.1. TX MAC Registers 8.2. RX MAC Registers 8.3. Pause/PFC Flow Control Registers 8.4. Statistics Registers 8.5. Hard IP Registers
8.4. Statistics Registers x
8.4.1. Statistics Registers
1. About the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile Low Latency 50G Ethernet Intel® FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. Document Revision History for the F-Tile Low Latency 50G Ethernet Intel® FPGA IP User Guide

7.4. Transceiver Reconfiguration Signals

You access the Transceiver and Ethernet control and status registers of the Hard IP using the Transceiver and Ethernet reconfiguration interface respectively. Both interfaces are Avalon® memory-mapped interface.

The core uses Ethernet F-Tile IP as a PMA (transceiver) for 50G. You can find more information about the Ethernet F-Tile IP core in the Ethernet F-Tile IP User Guide. The transceivers require an SYS PLL to generate the high speed serial clock. Only one SYS PLL is required for the transceivers within a single F-Tile. If required, you can share the SYS PLLs with other transceivers in the design. This is because the SYS PLL does not reside within the core and it must be instantiated externally. The example design instantiates the core and the SYS PLL.

Table 13.  Transceiver Reconfiguration Interface Ports of the F-Tile Ethernet Hard IPAll interface signals are clocked by the reconfig_clk clock.
Signal Name Direction Width Description
reconfig_clk Input 1 Avalon® clock. The clock frequency is 100 MHz. All transceiver reconfiguration interface signals are synchronous to reconfig_clk .
reconfig_reset Input 1 Resets the Avalon® memory-mapped interface and all the registers to which it provides access.
Lane 0 Ports
i_reconfig_xcvr0_addr Input 18 Address bus.
i_reconfig_xcvr0_read Input 1 Read enable signal. Signal is active high.
i_reconfig_xcvr0_write Input 1 Write enable signal. Signal is active high.
i_reconfig_xcvr0_writedata Input 32 A 32-bit data write bus. reconfig_address specifies the address.
i_reconfig_xcvr0_byteenable Input 4 Byte enable Signal.
o_reconfig_xcvr0_readdata Output 32 A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
o_reconfig_xcvr0_waitrequest Output 1 Indicates the Avalon memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.
o_reconfig_xcvr0_readdata_valid Output 1 Indicates that the reconfig_readdata signal is valid.
Lane 1 Ports
i_reconfig_xcvr1_addr Input 18 Address bus.
i_reconfig_xcvr1_read Input 1 Read enable signal. Signal is active high.
i_reconfig_xcvr1_write Input 1 Write enable signal. Signal is active high.
i_reconfig_xcvr1_writedata Input 32 A 32-bit data write bus. reconfig_address specifies the address.
i_reconfig_xcvr1_byteenable Input 4 Byte enable Signal.
o_reconfig_xcvr1_readdata Output 32 A 32-bit data read bus. Drives read data from the specified address. Signal is valid after reconfig_waitrequest is deasserted.
o_reconfig_xcvr1_waitrequest Output 1 Indicates the Avalon memory-mapped interface is busy. Keep the reconfig_write or reconfig_read asserted until reconfig_waitrequest is deasserted.
o_reconfig_xcvr1_readdata_valid Output 1 Indicates that the reconfig_readdata signal is valid.
Table 14.  Ethernet Reconfiguration Interface Ports of the F-Tile Ethernet Hard IP
Port Name Direction Description
reconfig_eth_address[13:0] Input Address for the Ethernet control status registers.
reconfig_eth_read Input Read request signal for the Ethernet control status registers.
reconfig_eth_write Input Write request signal for the Ethernet control status registers.
reconfig_eth_readdata[31:0] Output Reads data from this port when the reconfig_eth_read signal is asserted.
reconfig_eth_writedata[31:0] Input Writes data to this port when the reconfig_eth_write signal is asserted.
reconfig_eth_waitrequest Output Indicates that the control and status interface is busy and unable to respond to read or write requests.
reconfig_eth_readdatavalid Output Indicates that the reconfig_eth_readdata signal is valid.
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