F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

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ID 750200
Date 11/29/2023
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. F-Tile 25G Ethernet Single-Channel Design Example 3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration 4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives 5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Generating the Design Example 1.3. Generating Tile Files 1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
1.2. Generating the Design Example x
1.2.1. Design Example Parameters
2. F-Tile 25G Ethernet Single-Channel Design Example x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Compilation 2.6. Hardware Testing
2.3. Functional Description x
2.3.1. Design Components
2.4. Simulation x
2.4.1. Testbench 2.4.2. Simulation Design Example Components 2.4.3. Test Case
2.6. Hardware Testing x
2.6.1. Test Procedure
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing
3.3. Functional Description x
3.3.1. Design Components
3.4. Simulation x
3.4.1. Testbench 3.4.2. Simulation Design Example Components 3.4.3. Test Case—Single-Channel Design Example with Dynamic Reconfiguration
3.5. Hardware Testing x
3.5.1. Test Procedure
1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide

2.6.1. Test Procedure

Follow these steps to test the design example in hardware:

  1. In the system console, navigate to the hwtest folder and run the command: source main.tcl to select a JTAG master. By default, the first JTAG master on the JTAG chain is selected. To select the JTAG master for Intel Agilex® 7 devices, run this command: set_jtag <number of appropriate JTAG master>. Example: set_jtag 1.
  2. Run the following commands in the system console to start the serial loopback test:
    Table 7.  Command Parameters
    Parameter Description Example Usage
    chkphy_status <link num> Displays the clock frequencies and PHY lock status. % chkphy_status 0 # Check status of link 0
    chkmac_stats <link num> Displays the values in the MAC statistics counters. % chkmac_stats 0 # Checks mac statistics counter of link 0
    clear_all_stats <link num> Clears the IP core statistics counters. % clear_all_stats 0 # Clears statistics counter of link 0
    start_gen <link num> Starts the packet generator. % start_gen 0 # Begin packet generation on link 0
    stop_gen <link num> Stops the packet generator. % stop_gen 0 # Stop packet generation on link 0
    loop_on <link num> Turns on internal serial loopback. % loop_on 0 # Turn on internal loopback on link 0
    loop_off <link num> Turns off internal serial loopback. % loop_off 0 # Turn off internal loopback on link 0
    reg_read <addr> Returns the IP core register value at <addr>. % reg_read 0x402 # Read IP CSR register at address 402 of link 0
    reg_write <addr> <data> Writes <data> to the IP core register at address <addr>. % reg_write 0x401 0x1 # Write 0x1 to IP CSR scratch register at address 401 of link 0
    1. Type loop_on <link num> to turn on the internal serial loopback mode.
    2. Type chkphy_status <link num> to check the status of the PHY. The TXCLK, RXCLK, and RX status should have the same values shown below for a stable link:
      Link: 0   Addr: 100
 RX PHY Register Access: Checking Clock Frequencies (KHz)

    TXCLK       :39062 (KHZ)
    RXCLK       :39063 (KHz)

Link: 0   Addr: 100
RX PHY Status Polling

Rx Frame Error            0x00000000

Tx PLL Lock Status        0x00000001

Rx Frequency Lock Status  0x00000001

RX PCS Ready              0x1

TX Lanes Stable           0x1

Deskewed Status           0x0

Link Fault Status         0x00000000
    3. Type clear_all_stats <link num> to clear TX and RX statistics registers.
    4. Type start_gen <link num> to begin packet generation.
    5. Type stop_gen <link num> to stop packet generation.
    6. Type chkmac_stats <link num> to read the TX and RX statistics counters. Make sure that:
      1. The transmitted packet frames match the received packet frames.
      2. No error frames are received.
    7. Type loop_off <link num> to turn off the internal serial loopback.
Figure 7. Sample Test Output—TX and RX Statistics Counters
Level Two Title