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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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2.4.3. Test Case
The simulation test case performs the following actions:
- Instantiates F-Tile 25G Ethernet Intel FPGA IP and F-Tile Reference and System PLL Clocks Intel® FPGA IP.
- Waits for RX clock and PHY status signal to settle.
- Prints PHY status.
- Sends and receives 10 valid data.
- Analyzes the results. The successful testbench displays "Testbench complete.".
The following sample output illustrates a successful simulation test run:
# # Waiting for RX alignment # RX deskew locked. # RX lane aligmnent locked # TX enabled # Applying reset # # ** Sending Packet 1... # ** Sending Packet 2... # ** Sending Packet 3... # ** Sending Packet 4... # ** Sending Packet 5... # ** Sending Packet 6... # ** Sending Packet 7... # ** Sending Packet 8... # ** Sending Packet 9... # ** Sending Packet 10... # ** Received Packet 1... # ** Received Packet 2... # ** Received Packet 3... # ** Received Packet 4... # ** Received Packet 5... # ** Received Packet 6... # ** Received Packet 7... # ** Received Packet 8... # ** Received Packet 9... # ** Received Packet 10... # ** # ** Testbench complete. # **