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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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2.4.2. Simulation Design Example Components
File Name | Description |
---|---|
Testbench and Simulation Files | |
basic_avl_tb_top.v | Top-level testbench file. The testbench instantiates the DUT, performs Avalon® memory-mapped configuration on design components and client logic, and sends and receives packet to or from the F-Tile 25G Ethernet Intel FPGA IP. |
Testbench Scripts | |
run_vsim.do | The ModelSim script to run the testbench. |
run_vcs.sh | The Synopsys VCS* script to run the testbench. |
run_xcelium.sh | The Cadence Xcelium* script to run the testbench. |