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1. Quick Start Guide
2. F-Tile 25G Ethernet Single-Channel Design Example
3. F-Tile 25G Ethernet Single Channel Design Example with Dynamic Reconfiguration
4. F-Tile 25G Ethernet Intel FPGA IP Design Example User Guide Archives
5. Document Revision History for F-Tile 25G Ethernet Intel® FPGA IP Design Example User Guide
1.1. Directory Structure
1.2. Generating the Design Example
1.3. Generating Tile Files
1.4. Simulating the F-Tile 25G Ethernet Intel FPGA IP Design Example Testbench
1.5. Compiling and Configuring the Design Example in Hardware
1.6. Testing the F-Tile 25G Ethernet Intel FPGA IP Hardware Design Example
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1.2.1. Design Example Parameters
Parameter | Description |
---|---|
Example Design | Available example designs for the IP parameter settings. |
Example Design Files | The files to generate for the different development phase.
|
Generate File Format | The format of the RTL files for simulation—Verilog. |
Select Board | Supported hardware for design implementation. When you select an Intel FPGA development board, use device AGIB027R31B1E2V as the Target Device for design example generation. Agilex I-series Transceiver-SoC Dev Kit: This option allows you to test the design example on the selected Intel FPGA IP development kit. This option automatically selects the Target Device of AGIB027R31B1E2V. If your board revision has a different device grade, you can change the target device. None: This option excludes the hardware aspects for the design example. |