Nios® V Processor Software Developer Handbook

ID 743810
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.4.2.2. crt0 Initialization

The crt0 code block contains the C run-time initialization code—initialization instructions needed to enable execution of C or C++ applications. The Intel provided crt0 block performs the following initialization steps:

  1. Initializes instruction cache—If the processor has an instruction cache, this cache is initialized.
    Note: Platform Designer determines the processors that have instruction caches and configures these caches at system generation. The Nios® V processor tools insert the instruction-cache initialization code block if necessary.
  2. Initializes data cache—If the processor has a data cache, this cache is initialized. As with the instruction caches, this code is enabled if the processor has a data cache.
  3. Initializes exception vector (mtvec) and interrupt controller settings—The exception vector and interrupt controller settings are initialized as configured in the hardware design.
  4. Set the global pointer—The global pointer register is initialized.
  5. Sets the stack pointer—The stack pointer is initialized. You can configure the stack pointer address.
  6. Clears the .bss section—The .bss section is initialized to all zeros. You can set the .bss section address.
  7. Calls alt_load macros—If the application is designed to run from flash memory (the .text section runs from flash memory), the remaining sections are copied to volatile memory.
  8. Jumps to alt_main()—The processor jumps to the alt_main() function, which begins initializing the HAL BSP run-time library.

Note: If you use a third-party RTOS or environment for your BSP library file, the alt_main() function can be different than the one provided by Intel.

If you use a third-party compiler or library, the C run-time initialization behavior may differ from this description.

The crt0.S source file is generated when generating the Nios® V processor BSP under <bsp_dir>/HAL/src directory. The crt0 code includes initialization short-cuts only if you perform hardware simulations of your design. You can control these optimizations by the hal.enable_sim_optimize setting.

For more information about the hal.enable_sim_optimize BSP setting, refer to Settings Managed by Nios V Processor Board Support Package Editor.