F-Tile Triple-Speed Ethernet Intel® FPGA IP User Guide

ID 741328
Date 4/03/2023
Public

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7.1.1.2. Clock Enabler Signals

Table 48.  Clock Enabler Signals
Name I/O Description
tx_clkena I Clock enable from the PHY IP. When you turn on the Use clock enable for MAC parameter, this signal is used together with tx_clk and rx_clk to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. 12
rx_clkena I Clock enable from the PHY IP. When you turn on the Use clock enable for MAC parameter, this signal is used together with tx_clk and rx_clk to generate 125 MHz, 25 MHz, and 2.5 MHz clocks. 13
12

For configurations without internal FIFO, this signal is called tx_clkena_<n>.

13

For configurations without internal FIFO, this signal is called rx_clkena_<n>.