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1. About this Document
2. Introduction
3. Nios® V Processor Hardware System Design with Intel® Quartus® Prime Pro Edition and Platform Designer
4. Nios® V Processor Software System Design
5. Nios® V Processor Configuration and Booting Solutions
6. Nios® V Processor - Using the MicroC/TCP-IP Stack
7. Nios® V Processor Debugging, Verifying, and Simulating
8. Document Revision History for the Nios® V Embedded Processor Design Handbook
5.1. Introduction
5.2. Linking Applications
5.3. Nios® V Processor Booting Methods
5.4. Introduction to Nios® V Processor Booting Methods
5.5. Nios® V Processor Booting from Configuration QSPI Flash
5.6. Nios V Processor Booting from On-Chip Memory (OCRAM)
5.7. Summary of Nios V Processor Vector Configuration and BSP Settings
7.4.1. Prerequisites
7.4.2. Setting Up and Generating Your Simulation Environment in Platform Designer
7.4.3. Creating Nios V Processor Software
7.4.4. Generating Memory Initialization File
7.4.5. Generating System Simulation Files
7.4.6. Running Simulation in the QuestaSim Simulator Using Command Line
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6.4.1. Hardware and Software Requirements
To use a µC/OS-II and µC/TCP-IP program on an Intel FPGA requires the following hardware and software:
- Intel® Quartus® Prime software version 22.1 or later
- One of the supported Intel FPGA devices
- The example designs are implemented on Intel Arria 10 SoC development kit
- Intel FPGA Download Cable II
- RJ-45 connected Ethernet cable on the same network as the PC development host
You must install the necessary open-source tools and connect your development board to a host PC on the Ethernet and USB/JTAG ports. For open-source tools, refer to Setting Up Open-Source Tools.
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