Arria V GZ Avalon-MM Interface for PCIe Solutions: User Guide

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ID 723696
Date 5/21/2017
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Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Design Example 3. Parameter Settings 4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Transceiver PHY IP Reconfiguration 9. Design Implementation 10. Throughput Optimization 11. Additional Features 12. Debugging B. Lane Initialization and Reversal C. Document Revision History
1. Datasheet x
1.1. Arria® V GZ Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Design Example x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Understanding Simulation Log File Generation 2.4. Running a Gate-Level Simulation 2.5. Simulating the Single DWord Design 2.6. Generating Synthesis Files 2.7. Creating a Quartus® Prime Project 2.8. Compiling the Design 2.9. Programming a Device 2.10. Understanding Channel Placement Guidelines
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. Avalon Memory‑Mapped System Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 4.4. Clock Signals 4.5. Reset 4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.7. Hard IP Status Signals 4.8. Physical Layer Interface Signals
4.7. Hard IP Status Signals x
4.7.1. Hard IP Reconfiguration Interface
4.8. Physical Layer Interface Signals x
4.8.1. Hard IP Status Extension 4.8.2. Serial Data Signals 4.8.3. PIPE Interface Signals 4.8.4. Test Signals
4.8.2. Serial Data Signals x
4.8.2.1. Physical Layout of Hard IP in Arria V GZ Devices 4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
9. Design Implementation x
9.1. Making Analog QSF Assignments Using the Assignment Editor 9.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 9.3. Recommended Reset Sequence to Avoid Link Training Issues 9.4. SDC Timing Constraints
10. Throughput Optimization x
10.1. Throughput of Posted Writes 10.2. Throughput of Non-Posted Reads
11. Additional Features x
11.1. Configuration over Protocol (CvP) 11.2. Autonomous Mode 11.3. ECRC
11.2. Autonomous Mode x
11.2.1. Enabling Autonomous Mode 11.2.2. Enabling CvP Initialization
11.3. ECRC x
11.3.1. ECRC on the RX Path 11.3.2. ECRC on the TX Path
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
12.2. Link Training x
12.2.1. Debugging Link that Fails To Reach L0
C. Document Revision History x
C.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Design Implementation
10. Throughput Optimization
11. Additional Features
12. Debugging
B. Lane Initialization and Reversal
C. Document Revision History

5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface

You can use the CRA interface to send TLP requests. The Fmt and Type fields of the TLP Header provide the information required to determine the size of the remaining part of the TLP Header, and if the packet contains a data payload following the Header.

Figure 25. TLP Header Format

The CRA interface uses register addresses 0x2000, 0x2004, and 0x2008 to send TLPs, and register addresses 0x2010, 0x2014, and 0x2018 to check Completions. For details about these registers, refer to the table Root Port TLP Data Registers, 0x2000 - 0x2FFF. Below are examples of how to use Type 0 configuration TLPs to read from BAR0 and write to it.

  1. Use the CRA interface to read an uninitialized BAR0 using a Type 0 configuration TLP with the format as shown below:
         | fmt |   typ   |t|  tc |t|a|l|t|t|e|att| at|       length      |
     | 000b|  00100b |0|_ 0 _|0|0|0|0|0|0| 0 | 0 |_______ 001 _______|
     |________ req_id: 0000 _________|___ tag: 17 ___|lbe: 0 |fbe: f |
     |    bdf.bus  |bdf.dev|bdf.func|rsvd20|reg_no.ext|reg_no.low|rsv|
     |______ 01 ___|__ 00 _|___ 0 __|_ 0 __|___ 0 ____|___ 04 ___| 0 |
     04000001 0000170f 01000010

    To send the TLP using the CRA interface, do the following steps:

    1. Write 0x0400_0001 to CRA interface address 0x2000.
    2. Write 0x0000_170F to CRA interface address 0x2004.
    3. Write 0x0000_0001 to CRA interface address 0x2008 (Start of Packet).
    4. Write 0x0100_0010 to CRA interface address 0x2000.
    5. Write 0x0000_0000 to CRA interface address 0x2004.
    6. Write 0x0000_0002 to CRA interface address 0x2008 (End of Packet).

    Check the corresponding Completion using the CRA interface. The Completion TLP has four dwords, with the first three dwords as shown below, followed by one dword of uninitialized BAR0 value (which is 0xFFEF0010 in the following picture). 

        | fmt |   typ   |t|  tc |t|a|l|t|t|e|att| at|       length      |
    | 010b|  01010b |0|_ 0 _|0|0|0|0|0|0| 0 | 0 |_______ 001 _______|
    |_____ cpl_id: 0100 ___|cpl_status: 0|bcm: 0|__ byte_cnt: 004 __|
    |_____ req_id: 0000 ___|___ tag: 17 ___|rsvd20: 0| low_addr: 00 |
    4a000001 01000004 00001700 ffef0010

    To read the Completion using the CRA interface, do the following steps:

    1. Keep reading CRA interface address 0x2010 until bit [0] = 0x1 (indicating the Completion packet has arrived, and you can receive the SOP in the next step.
    2. Read CRA interface address 0x2014. The read data value is 0x4A00_0001.
    3. Read CRA interface address 0x2018. The read data value is 0x0100_0004.
    4. Read CRA interface address 0x2010. In this example, bits [1:0] = 0x2 (indicating that you will receive the EOP in the next step). If bits [1:0] = 0x0, the values read in the next two steps are still in the middle of the packet. In this case, you need to keep reading 0x2010, 0x2014, and 0x2018 after performing the next two steps.
    5. Read CRA interface address 0x2014. The read data value is 0x0000_1700.
    6. Read CRA interface address 0x2018. The read data value is BAR0's uninitialized value.
  2. Use the CRA interface to initialize BAR0 with 0xFFFF_FFFF using a Type 0 configuration TLP with the format as shown below:
        | fmt |   typ   |t|  tc |t|a|l|t|t|e|att| at|       length      |
    | 010b|  00100b |0|_ 0 _|0|0|0|0|0|0| 0 | 0 |_______ 001 _______|
    |________ req_id: 0000 _________|___ tag: 11 ___|lbe: 0 |fbe: f |
    |    bdf.bus  |bdf.dev|bdf.func|rsvd20|reg_no.ext|reg_no.low|rsv|
    |______ 01 ___|__ 00 _|___ 0 __|_ 0 __|___ 0 ____|___ 04 ___| 0 |
    44000001 0000110f 01000010 ffffffff

    To send the TLP using the CRA interface, do the following steps:

    1. Write 0x4400_0001 to CRA interface address 0x2000.
    2. Write 0x0000_110F to CRA interface address 0x2004.
    3. Write 0x0000_0001 to CRA interface address 0x2008 (Start of Packet).
    4. Write 0x0100_0010 to CRA interface address 0x2000.
    5. Write 0xFFFF_FFFF to CRA interface address 0x2004.
    6. Write 0x0000_0002 to CRA interface address 0x2008 (End of Packet).

    Check the corresponding Completion using the CRA interface. The Completion TLP has three dwords as shown below: 

        | fmt |   typ   |t|  tc |t|a|l|t|t|e|att| at|       length      |
    | 000b|  01010b |0|_ 0 _|0|0|0|0|0|0| 0 | 0 |_______ 000 _______|
    |_____ cpl_id: 0100 ___|cpl_status: 0|bcm: 0|__ byte_cnt: 004 __|
    |_____ req_id: 0000 ___|___ tag: 11 ___|rsvd20: 0| low_addr: 00 |
    0a000000 01000004 00001100

    To read the Completion using the CRA interface, do the following steps:

    1. Keep reading CRA interface address 0x2010 until bit [0] = 0x1 (indicating the Completion packet has arrived, and you can receive the SOP in the next step).
    2. Read CRA interface address 0x2014. The read data value is 0x0A00_0000.
    3. Read CRA interface address 0x2018. The read data value is 0x0100_0004.
    4. Read CRA interface address 0x2010. In this example, bits [1:0] = 0x2.
    5. Read CRA interface address 0x2014. The read data value is 0x0000_1100.

You can repeat Step 1 to read BAR0 after writing 0xFFFF_FFFF to it, and repeat Step 2 to configure the BAR0 address space.

Use the same method to configure BAR1, BAR2, BAR3, BAR4 and BAR5.

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