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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Precision Time Protocol Interface
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8. Document Revision History for the F-Tile Ethernet Multirate Intel FPGA IP User Guide
Document Version | Intel® Quartus® Prime Version | IP Version | Changes |
---|---|---|---|
2022.12.19 | 22.4 | 5.0.0 | Added the following in Parameters section:
|
2022.10.20 | 22.3 | 4.0.0 | Added the following:
Added the following in Interface Overview section:
Added the following in Parameters section.
Added the following in Configuration Registers section.
Added Document Archive section. |
2022.06.20 | 22.2 | 3.0.0 | Added the following:
|
2022.04.04 | 22.1 | 2.0.0 | Initial release. |