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2.1. Port Numbering Scheme
2.2. Clock Signals
2.3. Reset Signals
2.4. Fractured MAC Segmented Interface for FGT Transceivers
2.5. Fractured MAC Segmented Interface for FHT Transceivers
2.6. Fractured MAC Avalon ST Client Interface for FGT Transceivers
2.7. Fractured MAC Avalon ST Client Interface for FHT Transceivers
2.8. Fractured MII PCS-Only Interface for FGT Transceivers
2.9. Fractured MII PCS-Only Interface for FHT Transceivers
2.10. Fractured PCS66 Interface for OTN/FlexE for FGT Transceivers
2.11. Fractured PCS66 Interface for OTN/FlexE for FHT Transceivers
2.12. MAC Flow Control Interface
2.13. Status Interface
2.14. Avalon® Memory-Mapped Reconfiguration Interfaces
2.15. Precision Time Protocol Interface
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1.4. Device Speed Grade Support
The F-Tile Ethernet Multirate Intel® FPGA IP core supports the following speed grades for Intel® Agilex™ devices:
- Core speed grade: -1 or -2 or -3
Note: Intel recommends -1 or -2 core speed grades for IP core variation with PTP.
For OPNs AGIB041R29D1E2VR0, AGID041R29D1E2VR0, or any device density code of 041, the following applies for PTP variants:
- Only 10GE with PTP is supported in Advanced mode with a core speed grade of -2 or faster. Basic mode is not supported.
- 25GE with PTP, 50GE with PTP, 100GE with PTP, 200G with PTP and 400GE with PTP are not supported in either Basic or Advanced mode.
For information about the applicable device speed grades based on the target data rates, refer to the following tables in Intel® Agilex™ Device Data Sheet:
- Table: F-Tile FHT Transmitter and Receiver Data Rate Performance for Intel® Agilex™ Devices
- Table: F-Tile FGT Transmitter and Receiver Data Rate Performance for Intel® Agilex™ Devices
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