AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.2. PCB Best Practices

  1. Connect power (VDD) and ground (GND) pins directly to corresponding power planes on the PCB without passing through any resistor.
  2. Keep the thickness of your PCB dielectric layer to a minimum so that the VDD and GND planes create low inductance paths.
  3. Mount one low-ESR 0.1 uF decoupling capacitor at each VDD pin. Intel recommends smaller capacitors such as the 0402 package, as the insertion loss is lower. Place the capacitor closest to the VDD pin.
  4. Incorporate one capacitor with capacitance in the range of 4.7 uF to 10uF in the power supply decoupling. You can use an ultra-low ESR ceramic. Place the capacitor further away from the FPGA than the 0.1 uF VDD decoupling capacitors.
  5. Use specific best practises when designing around Low Dropout Regulators (LDOs), MOSFET and clock (CLK) signals to minimize noise couplings. The purpose is to isolate noise and yield the best signal integrity.
  6. Do not let signal lanes pass through voids. Use stitching vias around insufficient ground reference in congested spots.

In addition to the above, here are some tips on designing PCB layouts:

  1. Route the high-speed TMDS traces on the top layer to avoid the use of vias (and the introduction of their inductances). This allows for clean interconnects from the HDMI connectors to the redriver inputs and outputs. It is important to match the electrical length of these high-speed traces to minimize both inter-pair and intra-pair skew (Refer to HDMI 2.1 CTS requirements for the measurement).
  2. Place a solid ground plane next to the high-speed single layer to establish controlled impedance (targetted Z) for transmission link interconnects and provide a better low–inductance path for the return current flow.
  3. Route slower control signals on the bottom layer to allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias and therefore, higher insertion loss. Separate the signals with low voltage swing and single ended types from high speed differential pairs with larger (3x) spacing to minimize attenuation.
  4. Place a power plane next to the ground plane to create an additional high-frequency bypass capacitance.
  5. If you require an additional supply voltage plane or signal layer, add a second power/ground plane system to the stack to maintain symmetry. This action mechanically stabilises the stack and prevents it from warping. You can significantly increase the high-frequency bypass capacitance by placing the power and ground plane of each power system closer together.

HDMI 2.1 supports the power over cable assembly (PCA cables). Evaluate the voltage drop on the 5 V rail at both TX and RX. In general, the widening traces for 5 V rail can tolerate higher current load since nominal voltage remains at 5 V.

Evaluate the HDMI connector footprint carefully to ensure you use compliant connectors. Strap the Ground pins to the nearest ground plane and do not leave the pins dangling. A good ground reference is critical to have the desired impedance control.

Note: If there is significant change in Loss Profile, Intel recommends that you simulate on Advanced Link Analyzer (ALA) to optimize TX/RX settings based on actual system profiles.
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