AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

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ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.3.1. FPGA TX Settings

Intel recommends the settings in Table 6 for your FPGA TX. Both FPLL and ATXPLL apply. In general, ATX PLL has a slightly better margin than FPLL, although this may not be a dominant factor for Intel® Arria® 10 and Intel® Stratix® 10.

For a complete list of settings, refer to Transceiver User Guide.

Table 6.  FPGA TX Recommended Settings
Item Value
Vod output swing ctrl 30
Pre emp sign 1st post tap Fir post 1t neg
Pre emp sign 2nd post tap Fir post 2t neg
Pre emp switching ctrl 1st post tap 5
Pre emp switching ctrl 2nd post tap 0
Pre emp sign pre tap 1t Fir pre 1t post
Pre emp sign pre tap 2t Fir pre 2t neg
Pre emp switching ctrl pre tap 1t 0
Pre emp switching ctrl pre tap 2t 0
Slew rate ctrl Slew r5

Set TX slew rate to r5 to ensure all four TMDS data channels (three data channels and one clock) are within the 2 UI bonding requirements of Test Point 1 (TP1) and meet inter-lane skew requirements.

Your TX redriver settings are determined by your PCB design profile. Intel recommends a minimum VOD setting of 1.0 on the TX redriver.

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